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ee120a Lecture 17 - Datapath Components - Multipliers, ALU, Register Files (Slides 2x1 bw)

# Ee120a Lecture 17 - Datapath Components - Multipliers, ALU, Register Files (Slides 2x1 bw)

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1 Lecture 17 Datapath Components – Multipliers, ALU, Register Files Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Logic Design Datapath Components: Multipliers, ALU, Register Files EE120A Lecture 17 Lecture 17 Datapath Components – Multipliers, ALU, Register Files Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Multiplier – Array Style We can build a multiplier that mimics multiplication by hand square4 Notice that multiplying multiplicand by 1 is same as AND’ing with 1

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2 Lecture 17 Datapath Components – Multipliers, ALU, Register Files Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Multiplier – Array Style Generalized representation of multiplication by hand Note: before adding each shifted multiplicand and k-bit partial product, we change them to k+1 significant bits. Each resulting sum has k+1 bits; any carry out of the MSB of the k+1 bit sum is ignored. Lecture 17 Datapath Components – Multipliers, ALU, Register Files Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Binary Multiplication Observe, muliplication of binary numbers is equivalent to bitwise AND operation in partial product calculation
3 Lecture 17 Datapath Components – Multipliers, ALU, Register Files Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Multiplier Implementation Method 1 – Sequential Sequential multipliers use a single adder and a register to accumulate the partial products. Lecture 17 Datapath Components – Multipliers, ALU, Register Files Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Multiplier Method 2: Array Style (combinational ) (1/2)

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4 Lecture 17 Datapath Components – Multipliers, ALU, Register Files Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Multiplier Method 2: Array Style (combinational ) (2/2)
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Ee120a Lecture 17 - Datapath Components - Multipliers, ALU, Register Files (Slides 2x1 bw)

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