ee120a Lecture 15 - Datapath Components - Comparators, Counters, Timers (Slides 2x1 bw)

# Ee120a Lecture 15 - Datapath Components - Comparators, Counters, Timers (Slides 2x1 bw)

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Unformatted text preview: 1 Lecture 15 Datapath Components – Comparators, Counters, Timers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Logic Design Datapath Components Comparators, Counters, Timers EE120A Lecture 15 Lecture 15 Datapath Components – Comparators, Counters, Timers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Exclusive-OR (XOR) Gates XOR X Y X' Y X Y' ⊕ = ⋅ + ⋅ ≜ Exclusive-OR (XOR) Gate – 2-input gate whose output is ‘1’ if inputs are different Exclusive-NOR (XNOR) Gate – 2-input gate whose output is ‘1’ if inputs are the same XNOR (X Y)' (X+Y') (X'+Y) ⊕ = ⋅ ≜ a) XOR as AND-OR circuit b) XOR as a three level NAND circuit NOTE: XOR and XNOR are not basic functions of boolean algebra and most technologies cannot perform XOR, XNOR directly Recall: 2 Lecture 15 Datapath Components – Comparators, Counters, Timers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Parity Circuits Odd-Parity Circuit : output = 1 if odd number of 1’s in the inputs a) daisy-chain connection b) tree structure which is faster than a) Even-Parity Circuit : output = 1 if even number of 1’s in the inputs (= negated Odd-Parity circuit) NOTE: Parity circuits are frequently used in error-detecting codes that use an extra bit (a parity bit ) to detect errors in transmission or storage Lecture 15 Datapath Components – Comparators, Counters, Timers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Comparators (parallel) s N-bit equality comparator (parallel) : Outputs 1 if two N-bit numbers are equal s 4-bit equality comparator with inputs A and B s a3 must equal b3, a2 = b2, a1 = b1, a0 = b0 s Two bits are equal if both 1, or both 0 s eq = (a3b3 + a3’b3’) * (a2b2 + a2’b2’) * (a1b1 + a1’b1’) * (a0b0 + a0’b0’) s Recall that XNOR outputs 1 if its two input bits are the same s eq = (a3 xnor b3) * (a2 xnor b2) * (a1 xnor b1) * (a0 xnor b0) a3 b3 a2 b2 a1 b1 a0 b0 eq (a) (b) a3 a2 a1 a0 b3 eq b2 b1 b0 4-bit equality comparator a 0110 = 0111 ? 1 1 1 1 1 1 1 1 3 Lecture 15 Datapath Components – Comparators, Counters, Timers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside 8-bit Comparator (Lab 5) This is an 8-bit comparator I’ve utilized in Lab 5 implementation Lecture 15 Datapath Components – Comparators, Counters, Timers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Comparators (iterative) Iterative circuits (as 1 bit adders) are well suited for problems that can be solved by a simple iterative algorithm: 1. Set C to its initial value and set i to 0 2. Use C i and P i to determine the values of PO i and C i+1 3. Increment i 4. If i < n , goto step 2 NOTE: The cascading signals need time to “ripple” from the leftmost to the rightmost module. They are slower than parallelThe cascading signals need time to “ripple” from the leftmost to the rightmost module....
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## This note was uploaded on 07/13/2011 for the course EE 120a taught by Professor Roman during the Spring '11 term at Cornell.

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Ee120a Lecture 15 - Datapath Components - Comparators, Counters, Timers (Slides 2x1 bw)

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