ee120a Lecture 14 - Datapath Components - Adders (Slides 2x1 bw)

Ee120a Lecture 14 - Datapath Components - Adders (Slides 2x1 bw)

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1 Lecture 14 Datapath Components - Adders Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Logic Design Datapath Components ADDERS EE120A Lecture 14 Lecture 14 Datapath Components - Adders Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Adders s Adds two N-bit binary numbers s 2-bit adder: adds two 2-bit numbers, outputs 3-bit result s e.g., 01 + 11 = 100 (1 + 3 = 4) s Can we design it using combinational design process? But it doesn’t work well for reasonable-size N s Why not? 0 1 0 1 1 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 s0 0 1 0 1 1 0 1 0 s1 0 0 1 1 0 1 1 0 c 0 0 0 0 0 0 0 1 b0 0 1 0 1 0 1 0 1 b1 0 0 1 1 0 0 1 1 a1 0 0 0 0 0 0 0 0 Inputs Outputs a0 0 0 0 0 1 1 1 1
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Lecture 14 Datapath Components - Adders Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Why Adders Aren’t Built Using Standard Combinational Design Process s Truth table too big s 2-bit adder’s truth table shown s Has 2 (2+2) = 16 rows s 8-bit adder: 2 (8+8) = 65,536 rows s 16-bit adder: 2 (16+16) = ~4 billion rows s 32-bit adder: . .. s Big truth table with numerous 1s/0s yields big logic s Plot shows number of transistors for N-bit adders, using state-of-the-art automated combinational design tool 0 1 0 1 1 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 s0 0 1 0 1 1 0 1 0 s1 0 0 1 1 0 1 1 0 c 0 0 0 0 0 0 0 1 b0 0 1 0 1 0 1 0 1 b1 0 0 1 1 0 0 1 1 a1 0 0 0 0 0 0 0 0 Inputs Outputs a0 0 0 0 0 1 1 1 1 Q: Predict the number of transistors for a 16-bit adder A: 1000 transistors for N=5, doubles for each increase of N. So transistors = 1000*2 (N-5) . Thus, for N=16, transistors = 1000*2 (16-5) = 1000*2048 = 2,048,000. Way too many! a 10000 8000 6000 4000 2000 0 1 2 3 4 5 N 6 7 8 Transistors Lecture 14 Datapath Components - Adders Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Alternative Method to Design an Adder: Imitate Adding by Hand s Alternative adder design: mimic how people do addition by hand s One column at a time s Compute sum, add carry to next column 1 1 1 1 + 0 1 1
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Ee120a Lecture 14 - Datapath Components - Adders (Slides 2x1 bw)

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