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ee120a Lecture 13 - Hardware Testing of Logic Circuits (Slides 2x1 bw)

Ee120a Lecture 13 - Hardware Testing of Logic Circuits (Slides 2x1 bw)

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1 Lecture 13 Hardware Testing of Logic Circuits Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Logic Design Hardware Testing of Logic Circuits EE120A Lecture 13 Lecture 13 Hardware Testing of Logic Circuits Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Scan Capability An important flip-flop’s function for logic circuit testing is scan capability . In a nutshell, it is a facility to drive a flip-flop’s D input with an alternate source of data during device testing. When all of the flip-flops are put into testing mode, a test pattern can be “scanned in” using alternate data inputs. After the test pattern is loaded, the flip-flops are put back into “normal” mode, and all of the flip-flops are clocked normally. After one or more clock ticks, the flip-flops are put back into testing mode, and the results are “scanned out”.
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2 Lecture 13 Hardware Testing of Logic Circuits Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside D Flip-Flop with Enable Example : if EN is asserted, the external input D is selected; if EN is negated, the current output is used a) Circuit design b) Logic table c) symbol Positive edge triggered D flip-flop Lecture 13 Hardware Testing of Logic Circuits Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside D Flip-Flop with Scan Example : This is nothing more than a D flip-flop with a 2-input multiplexer on the D input. a) Circuit design b) Logic table c) symbol Positive edge triggered D flip-flop When the TE ( test enable ) input is negated, the circuit behaves like an ordinary D flip-flop.
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