ee120a Lecture 11 - Datapath Components - Registers (Slides 2x1 bw)

Ee120a Lecture 11 - Datapath Components - Registers (Slides 2x1 bw)

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1 Lecture 11 Datapath Components - Registers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Logic Design Datapath Components REGISTERS EE120A Lecture 11 Lecture 11 Datapath Components - Registers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Introduction s Previous Lectures : Introduced increasingly complex digital building blocks s Gates, multiplexors, decoders, basic registers, and controllers s Controllers good for systems with control inputs/outputs s Control input: Single bit (or just a few), representing environment event or state s e.g., 1 bit representing button pressed s Data input: Multiple bits collectively representing single entity s e.g., 7 bits representing temperature in binary s Need building blocks for data s Datapath components , aka register-transfer-level (RTL) components, store/transform data s Put datapath components together to form a datapath s Later we will combine controller and datapaths into “processors”
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2 Lecture 11 Datapath Components - Registers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Registers s Can store data, very common in datapaths s Basic register: Loaded every cycle s Useful for implementing FSM -- stores encoded state s For other uses, may want to load only on certain cycles Combinational logic State register s1 s0 n1 n0 x b clk I3 I2 I1 I0 Q3 Q2 Q1 Q0 reg(4) Basic register loads on every clock cycle load How to extend to only load on certain cycles? a D Q D Q D Q D Q I2 I3 Q2 Q3 Q1 Q0 I1 I0 clk 4-bit register Lecture 11 Datapath Components - Registers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Multiplexors i0 i1 s d MUX 2 x 1 Enable signal s controls which of the inputs appear at d s i1 i0 d Recall :
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3 Lecture 11 Datapath Components - Registers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Register with Parallel Load s Add 2x1 mux to front of each flip-flop s Register’s load input selects mux input to pass s Either existing flip-flop value, or new value to load 1 0 D Q Q3 I3 1 0 D Q Q2 I2 1 0 Q Q1 I1 1 0 D Q Q0 I0 load = 0 1 0 2 1 D Q I3 load load 1 0 D Q I2 1 0 D Q I1 1 0 D Q I3 1 0 D Q I2 1 0 D Q I1 1 0 D Q I0 load = 1 (b) (c) (a) 1 0 D Q I0 I3 I2 I1 I0 D Enable, s Lecture 11 Datapath Components - Registers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside Basic Example Using Registers (1/2) Example 1 : This example will show how registers load simultaneously on clock cycles s Notice that all load inputs set to 1 in this example -- just for demonstration purposes Q3 Q2 Q1 Q0 a3 a2 a1 a0 I3 I2 I1 I0 Q3 Q2 Q1 Q0 I3 ld 1 I2 I1 I0 ld 1 ld 1 Q3 Q2 Q1 Q0 I3 I2 I1 I0 R1 R0 R2 clk
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4 Lecture 11 Datapath Components - Registers Instructor: Roman Chomko EE120A Logic Design, 10U Electrical Engineering University of California - Riverside
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This note was uploaded on 07/13/2011 for the course EE 120a taught by Professor Roman during the Spring '11 term at Cornell University (Engineering School).

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Ee120a Lecture 11 - Datapath Components - Registers (Slides 2x1 bw)

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