ECE 315 Homework 10
Due 11:15am, November 30, 2007
in the drop box
1.
(CMOS static logic and transistor sizing)
Sketch a CMOS realization for the function
Y=(A+B(C+D))’
in full complementary CMOS logic.
Give the simple
W/L
ratios for all transistors
such that the worstcase
t
pHL
and
t
pLH
of the logic gate match those of the inverter with
(W/L)
PMOS
=6/2
and
(W/L)
NMOS
=3/2.
We will use this
W/L
notation for the entire homework. (10 pts)
2.
(Self loading in transistor sizing)
For a full static CMOS circuits that implement the function of
V
out
= (ABCD)’
.
(a)
In PDN, if each transistor can be approximated with a resistor proportional to
L/W
(largesignal
R
ON
) and the ONLY capacitive load at the drain
C
D
proportional to
WL
, express the time
constant when the four transistors are of identical minimal sizes of
W/L =3
λ
/2
(in which case,
R
ON
=R
m
,
and
C
D
=C
m
).
Assume the output has no additional capacitive loading, and the Miller
effect has already been included in
C
D
.
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 Fall '07
 SPENCER
 Microelectronics, Transistor, pts, Logic gate, CMOS static logic, logic gate match

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