exam2002

# exam2002 - VLSI Architecture Design Course(048853 Final...

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VLSI Architecture Design-final Exam July 4, 2002 Page # 1 VLSI Architecture Design Course (048853) Final Exam July 4 th , 2002 Electrical engineering Department Student name: _____________________ Student number: _______________ This exam contains TWO questions. The exam duration is 2:30 hours. Please fill the answers ON THE EXAM forms. Please explain or provide a formula for each computation! TAKE YOUR TIME, READ THE QUESTIONS THOUROUGHLY, UNDERSTAND THE CONTENT AND ONLY THAN START TO ANSWER Good luck! Q1 Q2 Total

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VLSI Architecture Design-final Exam July 4, 2002 Page # 2 Question 1 (50%) A microprocessor system is given (see Figure 1). The system contains a CPU with a given CPI 1 (for 100% cache hit rate), frequency of operation f 1 , a 256KB cache with 0 access time (CPU-to-cache) and an Hit Rate (HR) =99% for SPECint_base2000 (assume 1 cache access per instruction), and a memory system. The cache is a blocking cache, so none of the misses overlap. The access frequency to memory is F BUS =300Mhz and the data access time (request-to-data) is L BUS =10 bus cycles. Performance vs. frequency measurements were performed and the results are shown in Figure 2. Performance (SPECint_base2000) 530 640 1.5 Ghz 1.6 Ghz 1.7 Ghz 1.8 Ghz 1.9 Ghz 2.0 Ghz Figure 2 Figure 1 CPU Freq=f 1 , CPI=CPI 1 256KB Cache 99% Cache Hit Rate Memory 100% hit rate 300Mhz, 10 cycle round trip 0 cycle round trip
VLSI Architecture Design-final Exam July 4, 2002 Page # 3 QUESTIONS: A. Specify in a formula the contribution of the compute time and the memory time to the total execution time. B. Calculate the processor’s CPI 1 , (for 100% cache hit rate), using the system characteristics and the performance graph (Figure 2).

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VLSI Architecture Design-final Exam July 4, 2002 Page # 4 C. The Cache size was increased to 512KB. Figure 3 shows the performance vs. frequency of the system with 512KB cache. What is the Cache Hit Rate (HR 2 ) of the new cache?
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