Intel_8086

Intel_8086 - 8086 16-BIT HMOS MICROPROCESSOR 8086 8086-2...

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September 1990 Order Number: 231455-005 8086 16-BIT HMOS MICROPROCESSOR 8086/8086-2/8086-1 Y Direct Addressing Capability 1 MByte of Memory Y Architecture Designed for Powerful Assembly Language and Efficient High Level Languages Y 14 Word, by 16-Bit Register Set with Symmetrical Operations Y 24 Operand Addressing Modes Y Bit, Byte, Word, and Block Operations Y 8 and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal Including Multiply and Divide Y Range of Clock Rates: 5 MHz for 8086, 8 MHz for 8086-2, 10 MHz for 8086-1 Y MULTIBUS System Compatible Interface Y Available in EXPRESS — Standard Temperature Range — Extended Temperature Range Y Available in 40-Lead Cerdip and Plastic Package (See Packaging Spec. Order ± 231369) The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations to achieve high performance levels. 231455–1 Figure 1. 8086 CPU Block Diagram 231455–2 40 Lead Figure 2. 8086 Pin Configuration
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8086 Table 1. Pin Description The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ‘‘Local Bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus buffers). Symbol Pin No. Type Name and Function AD 15 –AD 0 2–16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T 1 ), and data (T 2 ,T 3 W 4 ) bus. A 0 is analogous to BHE for the lower byte of the data bus, pins D 7 –D 0 .Itis LOW during T 1 when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A 0 to condition chip select functions. (See BHE .) These lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ‘‘hold acknowledge’’. A 19 /S 6 , 35–38 O ADDRESS/STATUS: During T 1 these are the four most significant address lines for memory operations. During I/O operations these A 18 /S 5 , lines are LOW. During memory and I/O operations, status information A 17 /S 4 , is available on these lines during T 2 3 W 4 . The status of the A 16 /S 3 interrupt enable FLAG bit (S 5 ) is updated at the beginning of each CLK cycle. A 17 /S 4 and A 16 /S 3 are encoded as shown. This information indicates which relocation register is presently being used for data accessing. These lines float to 3-state OFF during local bus ‘‘hold acknowledge.’’ A 17 /S 4 A 16 /S 3 Characteristics 0 (LOW) 0 Alternate Data 0 1 Stack 1 (HIGH) 0 Code or None 1 1 Data S 6 is 0 (LOW) BHE /S 7 34 O BUS HIGH ENABLE/STATUS: During T 1 the bus high enable signal (BHE ) should be used to enable data onto the most significant half of the data bus, pins D 15 8 . Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T 1 for read, write, and interrupt
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Intel_8086 - 8086 16-BIT HMOS MICROPROCESSOR 8086 8086-2...

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