t1_fall02_sol

t1_fall02_sol - EE 4743 Test#1 – Fall 2002 Solutions 1(15...

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Unformatted text preview: EE 4743 Test #1 – Fall 2002 Solutions 1. (15 pts) On the diagram below, complete the timing diagram for the Y output for all clock cycles. D Q C Q’ R Y CLK D R CLK Y R D Reset keeps low Clock in a ‘1’ Reset brings low Clock in a ‘1’ OR gate feedback keeps Dff input high, clocking in ‘1’s Low true, async reset D Q C Q’ R Y CLK D R CLK Y R D Reset keeps low Clock in a ‘1’ Reset brings low Clock in a ‘1’ OR gate feedback keeps Dff input high, clocking in ‘1’s Low true, async reset 2. (15 pts) On the waveforms below, complete the waveforms for State, ld, en, and Q. The FSM is controlling an UP counter . ld D Q 8 8 Q[7:0] D[7:0] FSM Clk Clk ld start en sclr en sclr Start? S0 S1 1 ASM ld en Start? S2 1 CLK Start State S0 en ld Q D 25 32 14 42 51 63 72 81 S1 S1 S1 S2 S2 ?? ?? ?? 14 15 16 17 ld D Q 8 8 Q[7:0] D[7:0] FSM Clk Clk ld start en sclr en sclr Start? S0 S1 1 ASM ld en Start? S2 1 CLK Start State S0 en ld Q D 25 32 14 42 51 63 72 81 S1 S1 S1 S2 S2 ?? ?? ?? 14 15 16 17 3. (15 pts) For the figure below: a. Give the maximum register-to-register delay. Show your work. Tcq + tmult+ tadder + tsu = 3 + 14 + 12 + 1 = 30 ns b. Modify the diagram to add one level of pipelining but still maintain the same functionality. Add the pipeline stage in the place that will improve the register-to-register delay the most ....
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t1_fall02_sol - EE 4743 Test#1 – Fall 2002 Solutions 1(15...

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