EEEEW

EEEEW - 09-1 09-1 Multicycle Pipeline Operations Material...

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Unformatted text preview: 09-1 09-1 Multicycle Pipeline Operations Material may be added to this set. Material Covered Section 3.7. Long-Latency Operations (Topics) Typical long-latency instructions: floating point Pipelined v. non-pipelined execution units Initiation interval and latency Implementation of long-latency instructions. Timing diagrams 09-1 EE 4720 Lecture Transparency. Formatted 9:32, 21 March 2011 from lsli09. 09-1 09-2 09-2 Long-Latency Instructions (Operations) Common Long-Latency Instructions Fastest (shortestbut still longlatency): Floating-Point Add, Subtract, Conversions MIPS: add.d , sub.d , cvt.s.w (convert integer to float), etc. Intermediate Speed: Multiply MIPS: mul.d , mul.s . Slowest Speed: Divide, Modulo, Square Root MIPS: div.d , sqrt.d . 09-2 EE 4720 Lecture Transparency. Formatted 9:32, 21 March 2011 from lsli09. 09-2 09-3 09-3 Implementation of Long-Latency Instructions Implementation balances cost and performance. Low Cost: Unpipelined, Single Functional Unit, Data Recirculates Whole functional unit occupied by instruction during computation . . . . . . so it can execute only one instruction at a time. Intermediate Cost: Multiple Unpipelined Functional Units Functional units occupied by instruction during computation . . . . . . each can execute a different instruction. Cost a multiple of single-unit cost. Highest Cost: Pipelined Functional Unit Functional unit pipelined, at best each stage can hold a different instruction. Cost disadvantage depends on how unpipelined units implemented. 09-3 EE 4720 Lecture Transparency. Formatted 9:32, 21 March 2011 from lsli09. 09-3 09-4 09-4 Floating Point in Pipelined MIPS Implementation Typical Classroom Example Floating Point Functional Units FP Add Four stages, fully pipelined: Latency 3, Initiation Interval 1. Used for FP Add, FP Subtract, FP Comparisons, etc. FP Multiply Six stages, fully pipelined: Latency 5, Initiation Interval 1. Used for FP Multiply. FP Divide Twenty five stages, unpipelined: Latency 24, Initiation Interval 25. 09-4 EE 4720 Lecture Transparency. Formatted 9:32, 21 March 2011 from lsli09. 09-4 09-5 09-5 Floating-Point Pipeline Example floating unit implementation main features: Separate register file. Number of stages vary depending on functional unit. Floating-point writeback separate from integer writeback. format
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EEEEW - 09-1 09-1 Multicycle Pipeline Operations Material...

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