EEEFEFER

EEEFEFER - 10-1 10-1 Dynamic Scheduling This Set • Scheduling and Dynamic Execution Definitions From various parts of Chapter 4 • Description

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Unformatted text preview: 10-1 10-1 Dynamic Scheduling This Set • Scheduling and Dynamic Execution Definitions From various parts of Chapter 4. • Description of Two Dynamic Scheduling Methods Not yet complete. (Material below may repeat material above.) • Tomasulo’s Algorithm Basics Section 4.2 • Reorder Buffer and Tomasulo’s Algorithm Sections 4.2 and 4.8 plus non-text material. Non-text material. • Sample Problems 10-1 EE 4720 Lecture Transparency. Formatted 9:23, 25 April 2011 from lsli10. 10-1 10-2 10-2 Dynamic Scheduling Scheduling: Organizing instructions to improve execution efficiency. Static Scheduling: Organizing of instructions by compiler or programmer to improve execution efficiency. Statically Scheduled Processor: A processor that starts instructions in program order. It achieves better performance on code that had been statically scheduled. Processors covered in class up to this point were statically scheduled. Dynamic Scheduling: [processor implementation] A processor that allows instructions to start execution . . . . . . even if preceding instructions are waiting for operands. Static scheduling advantage: time and processing power available to scheduler (part of compiler). Dynamic scheduling advantage: can execute instructions after loads that miss the cache (they will take a long time to complete). (Compiler cannot often predict load misses.) Can make up for bad or inappropriate (targeted wrong implementation) static scheduling. 10-2 EE 4720 Lecture Transparency. Formatted 9:23, 25 April 2011 from lsli10. 10-2 10-3 10-3 Scheduling Examples Unscheduled Code add.s f0, f1, f2 sub.s f3, f0, f4 mul.s f5, f6, f7 lwc1 f8, 0(r1) addi r1, r1, 8 ori r2, r2, 1 10-3 EE 4720 Lecture Transparency. Formatted 9:23, 25 April 2011 from lsli10. 10-3 10-4 10-4 Unscheduled Code on Statically Scheduled (HP Chapter-3) MIPS Cycle: 1 2 3 4 5 6 7 8 9 10 11 add.s f0, f1, f2 IF ID A1 A2 A3 A4 WF sub.s f3, f0, f4 IF ID---------> A1 A2 A3 A4 WF mul.s f5, f6, f7 IF---------> ID M1 M2 M3 M4 M5 M6 WF lwc1 f8, 0(r1) IF ID-> EX ME WF addi r1, r1, 8 IF-> ID EX ME WB ori r2, r2, 1 IF ID EX ME WB Execution has four stall cycles. 10-4 EE 4720 Lecture Transparency. Formatted 9:23, 25 April 2011 from lsli10. 10-4 10-5 10-5 Statically Scheduled Code on Statically Scheduled MIPS Implementation Instructions reordered by compiler or programmer to remove stalls. Cycle: 1 2 3 4 5 6 7 8 9 10 11 add.s f0, f1, f2 IF ID A1 A2 A3 A4 WF lwc1 f8, 0(r1) IF ID EX ME WF mul.s f5, f6, f4 IF ID M1 M2 M3 M4 M5 M6 WF addi r1, r1, 8 IF ID EX ME WB ori r2, r2, 1 IF ID EX ME WB sub.s f3, f0, f4 IF ID A1 A2 A3 A4 WF Execution has zero stall cycles. 10-5 EE 4720 Lecture Transparency. Formatted 9:23, 25 April 2011 from lsli10. 10-5 10-6 10-6 Execution of unscheduled code on dynamically scheduled processor: Cycle: 1 2 3 4 5 6 7 8 9 10 11 add.s f0, f1, f2 IF ID Q RR A0 A1 A2 A3 WC sub.s f3, f0, f4 IF ID Q RR A0 A1 A2 A3 WC mul.s f5, f6, f7 IF ID Q RR M0 M1 M2 M3 M4 M5 M6 WC lwc1 f8, 0(r1) IF ID Q RR EA ME WB...
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This note was uploaded on 07/18/2011 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

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EEEFEFER - 10-1 10-1 Dynamic Scheduling This Set • Scheduling and Dynamic Execution Definitions From various parts of Chapter 4 • Description

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