lec04 - LECTURE - 04 Announcements Course web-page is up

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: LECTURE - 04 Announcements Course web-page is up http://web.cse.iitk.ac.in/~cs422/index.html Lecture scribe notes: HTML please lec-notesXY-1.html or lec-notesXY-2.html Images in directory “images/” lecXY-1-anything.ext or lecXY-2-anything.ext Please email to one of the TAs Extra classes? Topics so far... Quantifying computer performance Amdahl's law Performance equation, CPI Effect of cache misses on CPI This week: Instruction Set Architecture (ISA) Pipelining: concept and issues Instruction Set Instruction set is the interface between hardware and software Interface design Central part of any system design Allows abstraction/independence Challenges: Should be easy to use by the layer above Should allow efficient implementation by the layer below Software Hardware Interface (Instruction set) Instruction Set Architecture (ISA) Main focus of early designs (1970s, 1980s) Mutual dependence between ISA design and: Machine organization Example: caches Higher level languages and compilers (what instructions do they want?) Operating systems Example: atomic instructions, paging... The Design Space Instruction Operand(s) Result operand What operations? e.g. add, sub, and 1 How many explicit operands? e.g. 0, 1, 2, 3 2 Non-memory operands from where? e.g. stack, register 3 Memory-operand access modes e.g. direct, indexed 4 Type and size of operand e.g. word, decimal 5 Other design choices: determining branch conditions, instruction encoding Classes of ISAs Stack Push A Push B Add Pop C Accumulator Load A Add B Store C Register- memory Load R1, A Add R1, B Store C, R1 Register- register Load R1, A Load R2, B Add R3, R1, R2 Store C, R3 Memory- memory Add C, A, B Those which use registers are also called General-Purpose Register (GPR) architectures Register-register also called load-store GPR Advantages...
View Full Document

This note was uploaded on 07/14/2011 for the course CS 422 taught by Professor Hogakoi during the Spring '10 term at IIT Kanpur.

Page1 / 27

lec04 - LECTURE - 04 Announcements Course web-page is up

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online