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lec05 - LECTURE 05 DLX DLX pronounced eluxe D Has the...

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LECTURE - 05
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DLX DLX pronounced “D eluxe” Has the features of many recent experimental and commercial machines [ AMD 29K, DECstation 3100, HP 850, IBM 801, Intel i860, MIPS M/120A, MIPS M/1000, Motorola 88K, RISC I, SGI 4D/60, SPARCstation-1, Sun-4/110, Sun-4/260 ] /13 = 560 = DLX (Roman) Good architectural features (e.g. simplicity), easy to understand
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DLX Architecture: Registers and Data Types Has 32 32-bit GPRs: R0...R31 Also, FP registers 32 single precision: F0...F31 Or, 16 double precision: F0, F2, ... F30 Value of R0 is always ZERO! Data types: Integer: bytes, half-words, words FP: single/double precision
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DLX Memory Addressing Uses 32-bit, big-endian mode Addressing modes: Only immediate and displacement, with 16-bit fields Register deferred? Place zero in displacement field Absolute Use R0 for the register
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DLX Instruction Format Opcode (6) RS1 (5) RD (5) Immediate (16) I-type instruction: loads, stores, all immediates, conditional branch, jump register, jump and link register Opcode (6) RS1 (5) RS2 (5) Func (11) RD (5) R-type instruction: register-register ALU operations Opcode (6) Offset relative to PC (26) J-type instruction: jump, jump and link, trap and return
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