Lec06 - LECTURE 06 DLX Unpipelined Implementation Five cycles IF ID EX MEM WB Branch and store instructions 4 cycles only What is the CPI F branch

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LECTURE - 06
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DLX Unpipelined Implementation ± Five cycles: IF, ID, EX, MEM, WB ² Branch and store instructions: 4 cycles only ² What is the CPI? F branch ³ 0.12, F store ³ 0.05 ± Further reduction in CPI (without pipelining) ± ALU instructions can finish in 4 cycles too F ALU ³ 0.47 CPI ³´ 4.83 µ 0.47 ¶³ 4.36 Speedup ³ 4.83 · 4.36 ³ 1.1 CPI ³ 0.17 ¸ 4 ¹ 0.83 ¸ 5 ³´ 5 µ 0.17 ¶³ 4.83
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Some Remarks ± Any further reduction in CPI will likely increase cycle time ± Some hardware redundancies can be eliminated ² Use ALU for (PC+4) addition also ² Same I-cache and D-cache ± These are minor improvements. .. ² An alternative single-cycle implementation: ± Variation in amount of work ==> higher cycle time ± Hardware unit reuse is not possible
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The Basic Pipeline for DLX ± That is it? ± Complications: ² Resource conflicts, Register conflicts, Branch instructions ² Exceptions, Instruction set issues CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 I IF ID EX MEM WB I+1 IF ID EX MEM WB I+2 IF ID EX MEM WB I+3 IF ID EX MEM WB I+4 IF ID EX MEM WB
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The Pipelined Data-path ID/EX MEM/WB Instrn. mem PC 4 Add m u x Reg.
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This note was uploaded on 07/14/2011 for the course CS 422 taught by Professor Hogakoi during the Spring '10 term at IIT Kanpur.

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Lec06 - LECTURE 06 DLX Unpipelined Implementation Five cycles IF ID EX MEM WB Branch and store instructions 4 cycles only What is the CPI F branch

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