lec07 - LECTURE - 07 Recall: Data Hazards Have to be...

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Unformatted text preview: LECTURE - 07 Recall: Data Hazards Have to be detected dynamically, and pipeline stalled if necessary Instruction issue: process of moving the instruction from ID stage to EX For DLX, all data hazards can be checked before instruction issue Also, control for data forwarding can be determined This is good since instruction is suspended before any machine state is updated Pipeline Interlock for “Load” Opcode of IF/ID (IF/ID.IR0..5) Check for interlock Load Reg-Reg ALU ID/EX.IR11.15 == IF/ID.IR6..10 Load Reg-Reg ALU ID/EX.IR11.15 == IF/ID.IR11..15 Load Load, store, ALU immediate, or branch ID/EX.IR11.15 == IF/ID.IR6..10 Opcode of ID/EX (ID/EX.IR0..5) Control Logic for Data- Forwarding Data forwarding always happens From ALU or data-memory output To ALU input, data-memory input, or zero- detection unit Which registers to compare? Compare the destination register field in EX/MEM and MEM/WB latches with the source register fields of IR in ID/EX and EX/MEM stages Control Hazard Result of branch instruction not known until end of MEM stage Naïve solution: stall until result of branch instruction is known That an instruction is a branch is known at the end of its ID cycle Note: “IF” may have to be repeated CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 Branch IF ID EX MEM WB Branch succ IF STALL STALL IF ID EX MEM WB Branch succ + 1 IF ID EX MEM Reducing the Branch Delay...
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This note was uploaded on 07/14/2011 for the course CS 422 taught by Professor Hogakoi during the Spring '10 term at IIT Kanpur.

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lec07 - LECTURE - 07 Recall: Data Hazards Have to be...

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