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lec11 - LECTURE 11 Instruction Level Parallelism Pipelining...

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LECTURE - 11
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Instruction Level Parallelism Pipelining achieves Instruction Level Parallelism (ILP) Multiple instructions in parallel But, problems with pipeline hazards CPI = Ideal CPI + stalls/instruction Stalls = Structural + Data (RAW/WAW/WAR) + Control How to reduce stalls? That is, how to increase ILP?
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Techniques for Improving ILP Loop unrolling Basic pipeline scheduling Dynamic scheduling, scoreboarding, register renaming Dynamic memory disambiguation Dynamic branch prediction Multiple instruction issue per cycle Software and hardware techniques
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Loop-Level Parallelism Basic block: straight-line code w/o branches Fraction of branches: 0.15 ILP is limited! Average basic-block size is 6-7 instructions And, these may be dependent Hence, look for parallelism beyond a basic block Loop-level parallelism is a simple example of this
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Loop-Level Parallelism: An Example Consider the loop: for(int i = 1000; i >= 1; i = i-1) { x[i] = x[i] + C; // FP } Each iteration of the loop is independent of other iterations Loop-level parallelism To convert it into ILP: Loop unrolling ( static , dynamic) Vector instructions
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The Loop, in DLX In DLX, the loop looks like: Loop: LD F0, 0(R1) // F0 is array element ADDD F4, F0, F2// F2 has the scalar 'C' SD 0(R1), F4 // Stored result
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