lec14 - LECTURE - 14 Dealing with Control Hazards Software...

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Unformatted text preview: LECTURE - 14 Dealing with Control Hazards Software techniques: Branch delay slots Software branch prediction Canceling or nullifying branches Misprediction rates can be high Worse if multiple issue per cycle Hence, hardware/dynamic branch prediction Branch Prediction Buffer PC --> Taken/Not-Taken (T/NT) mapping Can use just the last few bits of PC Prediction may be that of some other branch Ok since correctness is not affected Shortcoming of this prediction scheme: Branch mispredicted twice for each execution of a loop Bad if loop is small for(int i = 0; i < 10; i++) { x[i] = x[i] + C; } Two-Bit Predictor Have to mispredict twice before changing prediction Built in hysteresis General case is an n-bit predictor 0 to (2^n)-1 saturating counter 0 to (2^[n-1])-1 predict as taken 2^[n-1] to (2^n)-1 predict as not-taken Experimental studies: 2-bit as good as n-bit Implementing Branch Prediction Buffers Implementing branch prediction buffers Small cache accessed along with the instruction in IF Or, additional 2 bits in instruction cache...
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lec14 - LECTURE - 14 Dealing with Control Hazards Software...

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