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lec22 - LECTURE 22 Topics for Today Main memory Scribe for...

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LECTURE - 22
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Topics for Today Main memory Scribe for today?
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Main Memory DRAM versus SRAM DRAM is cheaper, but slower Reducing the number of pins At the cost of some performance Address = RAS + CAS Performance metrics: latency and bandwidth #cycles to send address #cycles to access a word #cycles to send the data word
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Main Memory Performance: One-Word Wide Memory Main Memory Cache CPU Bus (1 word) Bus (1 word) Suppose, #cycles to send address = 4 #cycles to access 1 word = 24 #cycles to send data word = 4 Cache line = 4 words What is the miss penalty? 4 x (4 + 24 + 4) = 128 cycles
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Technique-1: Wider Memory Main Memory Cache CPU Bus (2 words) Bus (1 word) Mux What is the miss penalty now? 2 x (4 + 24 + 4) = 64 cycles Disadvantages? Larger bus width (cost) Unit of memory addition is larger Read-modify-write for single-byte write, if error-correction present
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Technique-2: Interleaved-Memory Cache CPU Bus (1 word) Bus (1 word) Bank-1 Bank-2 Bank-3 Bank-4 What is the miss penalty now?
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