lec27 - matches that in the link register ± Beware of...

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LECTURE - 27
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Lecture Outline ± Synchronization mechanisms, and consistency models ± ± Scribe for today?
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Synchronization ± Required since communication is through shared memory ± Synchronization primitives ² Involve atomic read-and-write of a memory location ² Atomic exchange (with a register) ² Test-and-set ² Fetch-and-increment
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Synchronization and Coherence ± Atomic read-and-write causes problems with coherence ² Additional complexity ± Solution: push complexity to software! ² Pair of instructions ² Hardware support to tell if the two were executed atomically ² Load-linked and store-conditional ² Store fails if any intervening process switch, or coherence control operation
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Load-Linked/Store-Conditional ± Can implement atomic-exchange, fetch-and- increment ± Implementation issues: ² Use a link register to store address in previous load-linked instruction ² Process switch, or coherence control operation will clear the link register ² Store-conditional succeeds iff the address in it
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Unformatted text preview: matches that in the link register ± Beware of what (and how many) instructions between the pair Using Atomic Exchange for Spin-Locks ± Processor spins until it gets access to lock ± Useful to test if lock is already held, before trying to lock ± Even then, performance problems when multiple processors are trying to grab the lock ² Read/write misses generated by all processors ² Misses satisfied sequentially Barrier Locks ± Barrier is a synchronization primitive ² Can be used in programs ² Forces all processors to wait until the last one reaches the barrier ± Can be implemented with two spin-locks ² One to increment a counter ² One to hold the processors until barrier ± Can cause deadlock! ² Use count-down, or sense-reversing barrier Performance Optimizations ± Exponential back-off ± Queuing locks...
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lec27 - matches that in the link register ± Beware of...

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