sol2 - CS151B/EE116C Solutions to Homework #2 Problem (1)...

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1 CS151B/EE116C – Solutions to Homework #2 Problem (1) C.24 If there is no overflow, the circuitry shown in Figure C.5.10 is sufficient – the “Set” output from bit 31 (the sign bit) can be used as the “Less” input for bit 0. However, if there is an overflow, the inverse of the sign bit must be used as the “Less” input for bit 0. Both cases are handled correctly by the following circuitry (replacing the bottom part – bit 31 – of Figure C.5.10): 0 3 Result Operation a 1 CarryIn 0 1 Binvert b 2 Less Set Overflow detection Overflow 0 1 Ainvert “Less” input of bit 0
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2 Problem (2) C.25 Given that a number that is greater than or equal to zero is termed positive and a number that is less than zero is negative, inspection reveals that the last two rows of Figure 3.2 restate the information of the first two rows. Because A – B = A + (–B), the operation A – B when A is positive and B negative is the same as operation A + B when A is positive and B is positive. Thus the third row restates the conditions of the first. The second and fourth rows refer also to the same condition. Because subtraction of two’s complement numbers is performed by addition, a complete examination of overflow conditions for addition suffices to show also when overflow will occur for subtraction. Begin with the first two rows of Figure 3.2, and add rows for A and B with opposite signs. Build a table that shows all possible combinations of Sign and CarryIn to the sign bit position and derive the CarryOut, Overflow, and related information. Thus, Sign A Sign B Carry In Carry Out Sign of Result Correct Sign of Result Overflow ? Carry In XOR Carry Out Notes 0 0 0 0 0 0 No 0 0 0 1 0 1 0 Yes 1 Carries differ 0 1 0 0 1 1 No 0 |A| < |B| 0 1 1 1 0 0 No 0 |A| > |B| 1 0 0 0 1 1 No 0 |A| > |B| 1 0 1 1 0 0 No 0 |A| < |B| 1 1 0 1 0 1 Yes 1 Carries differ 1 1 1 1 1 1 No 0 From this table an Exclusive OR (XOR) of the CarryIn and CarryOut of the sign bit serves to detect overflow. When the signs of A and B differ, the correct sign of result is determined by the relative magnitudes of A and B, as listed in the Notes column. Problem (3) As shown in figure 4.24, ALUOp1 is the most significant bit of the two-bit ALUOp signal. The fault will cause ALUOp to be 00 for R-format instructions, when ALUOp is supposed to be 10 . Hence, the ALU will perform addition for ALL R-format instructions. Thus, the results of the instructions sub, and, or, slt
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This note was uploaded on 07/17/2011 for the course CS M151B taught by Professor Tamir during the Summer '11 term at UCLA.

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sol2 - CS151B/EE116C Solutions to Homework #2 Problem (1)...

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