Sol3 - CS151B/EE116C Solutions to Homework#3 Problem(1 0 6 jr rs rs 5 0 15 0x8 6 0x8 = 001000 Instruction jr has the same opcode as R-type

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1 CS151B/EE116C – Solutions to Homework #3 Problem (1) jr rs 0 rs 0 0x8 6 5 15 6 0x8 = 001000 Instruction jr has the same opcode as R-type instructions. However, jr can be distinguished from the other implemented R-type instructions based on the most significant bit of the funct field. Specifically, bit 5 of the jr instruction is 0 while, as shown in Figure 4.12, bit 5 of all the implemented R-type instructions is 1. Thus, bit 5 from the output of the instruction memory must be a new input to the main part of the control unit. A) Modifications to the datapath: Add a new multiplexor to determine whether the next PC value will be as before (the output of the PCSrc MUX) or the value of register R[Rs]. Bit 5 from the instruction memory must be connected to the main part of the control unit. (see next page) B) jrc (jr control) – controls the new multiplexor. C) R lw sw beq jr Op5 Op4 Op3 Op2 Op1 Op0 IR[5] RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0 jrc
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2 Read register 1 Read register 2 Write register Write data Write data Registers ALU Add Zero Read data 1 Read data 2 Sign extend 16 32 Instruction [31–0] ALU result Add ALU result M u x M u x M u x Address Data memory Read data Shift left 2 4 Read address Instruction memory PC 1 0 0 1 0 1 M u x 0 1 ALU control Instruction [5–0] Instruction [25–21] Instruction [31–26] Instruction [15–11] Instruction [20–16] Instruction [15–0] RegDst Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Control M u x 0 1 jrc Instruction [5] Problem (1) Datapath Problem (2) The fault is manifested only when the specified values of ALUSrcA and RegWrite differ in the same cycle. Examining the state diagram of Figure 5.37, one sees that states 2, 4, 6, 7, and 8 are impacted. In states 4 and 7, RegWrite is 1 and ALUSrcA should be 0. Instead, ALUSrcA will be 1 because of the fault. Neither state uses the output of the ALU. Furthermore, for both states 4 and 7, the succeeding state is state 0, and state 0 does not use the output of the ALUOut register. Therefore, changing the first ALU operand from PC to A in states 4 and 7 has no visible impact on correct execution. In states 2, 6, and 8 ALUSrcA is 1 and RegWrite should be 0. Instead, RegWrite will be 1 because of the fault. The following additional state change will occur in these states: R[IR 20. .16 ] ALUOut. Notice that for states 2, 6, and 8, the previous sate is stae 1, during which the branch target for the beq instruction is computed (regardless of the actual instruction being executed). Hence, during state 1, ALU is set to ALUOut PC + SignExt(IR 15. .0 || 00) where PC is the address of the next instruction. State 2 impacts lw and sw , but the fault is masked for lw because R[IR 20. .16 ] is overwritten with the proper value in state 4. Therefore, the user/programmer will observe the following incorrect behavior:
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3 1) When a sw instruction is executed, the value of the register specified in the Rt field will be overwritten by the value PC + 4 + SignExt(Instruction 15. .0 || 00), where PC is the address of the sw instruction and Instruction 15. .0 is the immediate field of the sw instruction.
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This note was uploaded on 07/17/2011 for the course CS M151B taught by Professor Tamir during the Summer '11 term at UCLA.

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Sol3 - CS151B/EE116C Solutions to Homework#3 Problem(1 0 6 jr rs rs 5 0 15 0x8 6 0x8 = 001000 Instruction jr has the same opcode as R-type

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