01_intro

01_intro - Moores Law Growth in Single Processor...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
CS151B 1.1 Moore’s Law # transistors / chip increases exponentially over time: ~doubles every two years transistor count feature size in micron 2011, Y. Tamir CS151B 1.2 Growth in Single Processor Performance 2011, Y. Tamir CS151B “single biggest change in the history of computing systems” “The Concurrency Revolution” Tilera TILE64 (2007) The Multicore “Revolution” 1.3 2011, Y. Tamir Processing Power in Cell Phones CS151B 1.4 Sanjay K. Jha, “Driving the Evolution of Wireless,” Qualcomm, March 2007. 2011, Y. Tamir
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Evolution of IBM Microprocessors CS151B 1.5 Ronald Kalla and Balaram Sinharoy, “POWER7: IBM's Next Generation Server Processor” 2011, Y. Tamir CS151B 1.6 IBM POWER6 introduced 2007 790 M transistors 65nm technology 4.7 GHz 2011, Y. Tamir IBM POWER7 released Feb 10 CS151B 1.7 • 45nm, SOI technology • 1.2B transistors Equivalent function of 2.7B eDRAM efficiency • Eight processor cores 12 execution units per core 4 Way SMT per core 32 Threads per chip 256KB L2 per core • 32MB on chip eDRAM shared L3 Ronald Kalla and Balaram Sinharoy, “POWER7: IBM's Next Generation Server Processor”. William J. Starke, “POWER7: IBM’s Next Generation, Balanced POWER Server Chip”, 2009. 2011, Y. Tamir CS151B 1.8 Intel Core-i7 (introduced 2008) 4 CPUs 9MB on-die cache 731 M transistors 45nm technology on-chip memory controller 2011, Y. Tamir
Background image of page 2
Intel Nehalem-EX (April 2010) CS151B 1.9 • 45nm technology • 2.3B transistors • 8 cores, 16 threads • 24MB shared L3 cache • 2 integrated memory controllers 2011, Y. Tamir CS151B 1.10 Tilera’s TILE64 Chip introduced 2007 •8 8 grid (64 CPUs) • five physical networks – 27 Tbps • 4.8 MB on-chip cache • 192 G 32-bit ops/sec at 1GHz each CPU: • 3-way VLIW • MMU – can run OS 2011, Y. Tamir CS151B 1.11 Tilera’s TILE-GX Chip introduced 2011 compared to TILE64: •8 8 grid (64 CPUs) • five physical networks – 27 Tbps • 4.8 MB on-chip cache • 192 G 32-bit ops/sec at 1GHz 2011, Y. Tamir Memory Controller Memory Control er Memory Control er Memory Control er Memory Control er Network I/O Eight 10Gb -or- 32 1Gb -or- Two 40Gb UART x2 USB x2 JTAG, I 2 C, SPI MiCA mPIPE MiCA 3 PCIe Interfaces Flexible I/O • 10 10 grid (100 CPUs) • 64-bit CPUs • 200 Tbs on-chip nets • 32 MB on-chip cache • 750 G 32-bits ops/sec Intel’s Single-chip Cloud Computer (SCC) CS151B 24 tiles, 2 cores/tile, P4 cores, 16K L1 $, 45nm technology “Knight’s Corner”, 50+ cores, 22nm technology, 2011 1.12 2011, Y. Tamir
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
NVIDIA Tesla GPU CS151B 2011, Y. Tamir 1.13 GPU Host CPU System Memory DRAM ROP L2 DRAM ROP L2 DRAM ROP L2 DRAM ROP L2 TPC Texture Uni t Tex L1
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 07/17/2011 for the course CS M151B taught by Professor Tamir during the Summer '11 term at UCLA.

Page1 / 15

01_intro - Moores Law Growth in Single Processor...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online