02_mips

02_mips - A Simple Processor Model Memory 2 The Central...

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CS151B 2.1 A Simple Processor Model y r o m e M s e c i v e D O / I 2 2 ) l a n o i t c e r i d i B ( a t a D s s e r d d A l o r t n o C U P C ) R I ( r e t s i g e R n o i t c u r t s n I ) C P ( r e t n u o C m a r g o r P e t a t S , s e d o C n o i t i d n o C h t a p a t a D s r e t s i g e R U L A ) e n i h c a M e t a t S ( r e l l o r t n o C e d o C - p O s e d o C n o i t i d n o C r e l l o r t n o C e t a t S e t i n i F k c o l C t e s e R Instruction Execution: 1. instruction fetch 2. instruction decode 3. operand fetch 4. execute 5. result store 6. next instruction 2011, Y. Tamir CS151B 2.2 The Central Processing Unit (CPU) CPU executes program instructions two major components: • datapath – data storage, data transformation, data transfers – key components: Arithmetic Logic Unit (ALU), registers, buses • control generates the signals telling the datapath what to do 2011, Y. Tamir CS151B 2.3 Instruction Interpretation Loop 2011, Y. Tamir CS151B 2.4 ISA Specification: M = (S, C, I) set of states: all storage “visible” to the program • memory: sizes of addressable units, minimum addressable unit little endian vs. big endian alignment requirements maximum size • registers sizes and types special purpose vs. general purpose all the instructions • instruction format (syntax) opcode – what operation to perform operand specifiers – location of operands and result(s) fixed size vs. variable size • instruction functionality (semantics) state transformation caused by the instruction: “supported data types”,
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02_mips - A Simple Processor Model Memory 2 The Central...

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