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03_single - A Simple Processor Model Memory 2 Components of...

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CS151B 3.1 A Simple Processor Model y r o m e M s e c i v e D O / I 2 2 ) l a n o i t c e r i d i B ( a t a D s s e r d d A l o r t n o C U P C ) R I ( r e t s i g e R n o i t c u r t s n I ) C P ( r e t n u o C m a r g o r P e t a t S , s e d o C n o i t i d n o C h t a p a t a D s r e t s i g e R U L A ) e n i h c a M e t a t S ( r e l l o r t n o C e d o C - p O s e d o C n o i t i d n o C r e l l o r t n o C e t a t S e t i n i F k c o l C t e s e R Instruction Execution: 1. instruction fetch 2. instruction decode 3. operand fetch 4. execute 5. result store 6. next instruction 2011, Y. Tamir CS151B 3.2 Components of Digital Systems combinational elements current outputs depend only on current inputs state elements storage wires/buses clocking methodology when state elements are read/written 2011, Y. Tamir CS151B 3.3 Edge-Triggered Clocking State element 1 State element 2 Combinational logic Clock cycle State element Combinational logic 2011, Y. Tamir CS151B 3.4 Designing a Processor – Analysis 1. instruction set datapath requirements – need precise semantics of each instruction all data transfers and transformations – datapath must include storage elements for ISA registers and may include additional storage elements – datapath must support each of the required data transfers (not necessarily in “one step”) – datapath must support each of the required data transformations (not necessarily in “one step”) 2011, Y. Tamir
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CS151B 3.5 Designing a Processor – Synthesis 2. select set of datapath components and establish clocking methodology 3. assemble datapath meeting the requirements 4. analyze implementation of each instruction to determine setting of control points implementing specified data transfers and transformation 5. assemble the control logic 2011, Y. Tamir CS151B 3.6 Key Steps of Instruction Execution on MIPS 1. send PC value to instruction memory and fetch instruction 2. increment PC to point to the next instruction in memory 3. read one or two registers 4. main alternatives: • perform an arithmetic or logical operation • access data memory (address computation) • compute branch/jump target 5. store value in register file (not for stores, branch, jump) 2011, Y. Tamir CS151B 3.7 Register Transfer Level (RTL) Description of Instruction Functionality: add sub add rd,rs,rt fetch M[[PC]] ; PC [PC]+4 ; NEXT ; R d [R s ]+[R t ] ; fetch M[[PC]] ; PC [PC]+4 ; NEXT ; R d [R s ] [R t ] ; sub rd,rs,rt 2011, Y. Tamir CS151B 3.8 Register Transfer Level (RTL) Description of Instruction Functionality: lw lw rt,imm16(rs) fetch M[[PC]] ; PC [PC]+4 ; NEXT ; R t M[[R s ]+((I 15 ) 16 || I 15. .0 )] ; positive immediate value: negative immediate value: 2011, Y. Tamir
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CS151B 3.9 MIPS Subset Implementation An Abstract View Data Register # Register # Register # PC Address Instruction Instruction memory Registers ALU Address Data Data memory Add Add 4 2011, Y. Tamir CS151B 3.10 1-Bit ALU Cell: AND, OR, ADD a b CarryIn CarryOut Operation 1 0 2 + Result 2 2011, Y. Tamir CS151B 3.11 32-bit ALU from 32 1-bit ALUs a0 Operation CarryIn ALU0 CarryOut b0 CarryIn a1 CarryIn ALU1 CarryOut
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03_single - A Simple Processor Model Memory 2 Components of...

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