04_multi

04_multi - Limitation of Single Cycle Implementation Single...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
CS151B 4.1 Single Cycle Implementation Read register 1 Read register 2 Write register Write data Write data Registers Add Read data 1 Read data 2 Sign extend 16 32 Instruction [31–0] Add ALU result M u x M u x M u x Address Data memory Read data Shift left 2 Shift left 2 4 Read address Instruction memory PC 1 0 0 1 1 0 M u x 0 1 M u x 0 1 ALU control Instruction [5–0] Instruction [25–21] Instruction [31–26] Instruction [15–11] Instruction [20–16] Instruction [15–0] RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Control Instruction [25–0] Jump address [31–0] 26 28 PC + 4 [31–28] ALU Zero ALU result 2011, Y. Tamir CS151B 4.2 Limitation of Single Cycle Implementation: Every Resource Used at Most Once Per Instructions resources: • instruction memory • data memory • adder for incrementing PC • ALU used by register-register R-type instructions • adder used for branch target computation • buses •e t c low resource utilization a poor (inefficient) design 2011, Y. Tamir CS151B 4.3 Limitation of Single Cycle Implementation: Same Execution time for Every Instruction slowest instruction determines execution time for all instructions low resource utilization low performance fetch instruction (inst memory) read from reg file perform ALU operation read from data memory write to register file fetch instruction (inst memory) read from reg file perform ALU operation write to register file lw add 2011, Y. Tamir CS151B 4.4 Multicycle Implementation instructions require multiple cycles to complete • during each cycle (step): – read from state elements – perform data transformation or data transfer – write to state elements • different instructions may take a different number of cycles state elements • program-visible (part of ISA) maintain values between instructions • implementation-specific (not part of ISA) maintain values between steps of same instruction 2011, Y. Tamir
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
CS151B 4.5 Multicycle Datapath Versus Single-Cycle Datapath Data Register # Register # Register # PC Address Instruction or data Memory Registers ALU Instruction register Memory data register ALUOut A B Data Data Register # Register # Register # PC Address Instruction Instruction memory Registers ALU Address Data Data memory Add Add 4 2011, Y. Tamir CS151B 4.6 Breaking an Instruction Into Multiple Cycles operations performed by instructions: fetch instruction, perform ALU operation, read from registers, write to registers, read from memory, write to memory compute next PC value, write to PC, etc • one or more operations per cycle • some operations must be performed sequentially • some operations may be performed in parallel hard constraint: two operations require the same (unique) resource they must be performed in different cycles 2011, Y. Tamir CS151B 4.7 Scheduling Dependent Operations into Cycles Should multiple dependent operations be scheduled to a single cycle?
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 19

04_multi - Limitation of Single Cycle Implementation Single...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online