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04s_cpe422_final_solution - The University of Alabama in...

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The University of Alabama in Huntsville ECE Department CPE/EE 422/522 01 Spring 2004 Final Exam Solution 1. (10 points) For the following circuit, find all tests for the faults g s-a-1 and g s-a-0. a b o h e j f g i k l n p m d c q r s a b c d r s g s-a-1 r g s-a-1 s g s-a-0 r g s-a-0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0-detect 0 1 0 0 1 0 1 0 0-detect 0 0 1 0 1 1 1 1 1 0-detect 0-detect 0 1 1 0 0 0 1–detect 0 0 0 0 1 1 1 0 0 1–detect 1–detect 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0-detect 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0-detect 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1-detect 0 0 2. (2 points) __Xilinx__ and __Altera__ are the two most prominent providers of field programmable gate arrays (FPGAs). 3. (2 points) _Transport_ delay and __inertial_ delay are the two types of delay provided for in VHDL. 4. (15 points) For the following SM chart: Draw a timing chart that shows the clock, the state (S0, S1 or S2), the inputs (X1, X2 and X3) and the outputs. The input sequence is X1 X2 X3 = 011, 101, 111, 010, 110, 101, 001. Assume that all state changes occur on the rising edge of the clock, and the inputs change on the falling edge of the clock.
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