04s_cpe422_hw5_solution

# 04s_cpe422_hw5_solut - The University of Alabama in Huntsville Electrical Computer Engineering CPE/EE 422/522 Spring 2004 Homework#5 Solution 5.1(a

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The University of Alabama in Huntsville Electrical & Computer Engineering CPE/EE 422/522 Spring 2004 Homework #5 Solution 5.1 (a) Construct an SM chart equivalent to the following state table. Test only one variable in each decision box. Try to minimize the number of decision boxes. (b) Write a VHDL description of the state machine based on the SM chart. Present Next State Output Z 1 Z 2 State X 1 X 2 =0 0 0 1 1 01 1X 1 X 2 0 0 1 1 1 S0 S3 S2 S1 S0 00 10 11 01 S1 S0 S1 S2 S3 10 10 11 11 S2 S3 S0 S1 S1 00 10 11 01 S3 S2 S2 S1 S0 00 00 01 01 (a) 0 X 1 X 2 X 1 Z 2 Z 1 X 2 Z 1 S2/ X 2 Z 2 X 2 S1/ X 2 X 2 Z 2 Z 1 Z 1 Z 2 X 2 X 1 X 1 S3/ Z 1 S0/ 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1

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(b) entity 5_1 is port (CLK, X1, X2 : in bit; Z1, Z2 ; out bit); end 5_1; architecture Smbehave of 5-1 is type states is {S0, S1, S2, S3}; signal state, next_state : states; begin process (X1, X2, state) begin Z1 <= ‘0’; Z2 <= ‘0’; case state is when S0 => if (X1 = ‘0’) then if (X2 = ‘0’) then next_state <= S3; else next_state <= S2; end if; else if (X2 = ‘0’) then Z1 <= ‘1’; Z2 <= ‘1’; next_state <= S1; else Z2 <= ‘1’;
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## This note was uploaded on 07/22/2011 for the course CPE 422 taught by Professor Staff during the Fall '09 term at University of Alabama - Huntsville.

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04s_cpe422_hw5_solut - The University of Alabama in Huntsville Electrical Computer Engineering CPE/EE 422/522 Spring 2004 Homework#5 Solution 5.1(a

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