05s_cpe422_hw2_solution - The University of Alabama in...

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The University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 2005 Homework #2 Solution 1.7 (20 points) Construct a clocked D flip-flop, triggered on the rising edge of CLK, using two transparent D latches and any necessary gates. Complete the following timing diagram, where Q1 and Q2 are latch outputs. Verify that the flip-flop output changes to D after the rising edge of the clock. D G Q Q CLK D G Q Q Q 1 Q 2 D D Q 1 Q 2 1.8 (30 points) A synchronous sequential network has one input and one output. If the input sequence 0101 or 0110 occurs, an output of two successive 1s will occur. The first of these 1s should occur coincident with the last input of the 0101 or 0110 sequence. The network should reset when the second 1 output occurs. For example, input sequence: X = 010011101010 101101… output sequence: Z = 000000000011 000000. . (a) Derive a Mealy state graph and table with a minimum number of states (6 states). NS Z PS X = 0 X = 1 X = 0 X = 1 S0 S1 S0 0 0 S1 S1 S2 0 0 S2 S3 S4 0 0 S3 S1 S5 0 1 S4 S5 S0 1 0 S5 S0 S0 1 1
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05s_cpe422_hw2_solution - The University of Alabama in...

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