05s_cpe422_hw4_solution

05s_cpe422_hw4_solution - The University of Alabama in...

This preview shows pages 1–2. Sign up to view the full content.

The University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 2005 Homework #4 Solution 2.3 In the following VHDL process A, B, C, and D are all integers that have a value of 0 at time = 10 ns. If E changes from ‘0’ to ‘1’ at time = 20 ns, specify the time(s) at which each signal will change and the value to which it will change. List these changes in chronological order (20, 20 + , 20 + 2 , etc.) p1:process begin A <= 0 after 10 ns; B <= 0 after 10 ns; C <= 0 after 10 ns; D <= 0 after 10 ns; wait on E; A <= 1 after 5 ns; B <= A + 1; C <= B after 10 ns; wait for 0 ns; D <= B after 3 ns; A <= A + 5 after 15 ns; B <= B + 7; wait; end process p1; ns delta A B C D E 0 +0 0 0 0 0 ‘0’ 20 +0 0 0 0 0 ‘1’ 20 +1 0 1 0 0 ‘1’ 20 +2 0 8 0 0 ‘1’ 23 +0 0 8 0 1 ‘1’ 25 +0 1 8 0 1 ‘1’ 28 +0 5 8 0 1 ‘1’ 2.8 (modified) An inhibited toggle flip-flop has inputs I0, T, and Reset, and outputs Q and QN. Reset is active high and overrides the action of the other inputs. The flip-flop works as follows. If I0 =

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 3

05s_cpe422_hw4_solution - The University of Alabama in...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online