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05s_cpe422_hw6_solution - The University of Alabama in...

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The University of Alabama in Huntsville Electrical and Computer Engineering CPE/EE 422/522 Spring 2005 Homework #6 Solution 5.3(a)(20), 5.6(c)(20), 5.12(20), 8.2(20), 8.8(20) 5.3 (a) For the following SM chart: Draw a timing chart that shows the clock, the state (S0, S1 or S2), the inputs (X1, X2 and X3) and the outputs. The input sequence is X1 X2 X3 = 011, 101, 111, 010, 110, 101, 001. Assume that all state changes occur on the rising edge of the clock, and the inputs change on the falling edge of the clock. 0 X 2 X 1 X 3 Z 2 Z 1 Z 3 X 2 S1/Z 1 X 1 S2/Z 1 S0/ 0 0 0 0 1 1 1 1 1 CLK X1 X2 STATE X3 S0 S2 Z1 Z2 Z3 S0 S2 S1 S2 S0 S1 5.6(c) For the given SM chart: Write a VHDL description of the system. S0/ X1 X2 Z1 S1/Z3 X3 Z2 0 1 0 X4 Z3 X4 S2/ 1 0 1 1 1 0 0
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library ieee; use ieee.std_logic_1164.all; entity SM_CHART5_6 is port (X1, X2, X3, X4, X5 : in std_logic; Z1, Z2, Z3 : out std_logic; CLK, RESET : in std_logic); end SM_CHART5_6; architecture BEHAVE of SM_CHART5_6 is type STATE_TYPE is (S0, S1, S2); signal STATE, NEXT_STATE : STATE_TYPE; begin process(X1, X2, X3, X4, X5, STATE) begin Z1 <= '0'; Z2 <= '0'; Z3 <= '0'; case STATE is when S0 => if (X1 = '0') then NEXT_STATE <= S0; else if (X2 = '0') then Z1 <= '1'; NEXT_STATE <= S1; else NEXT_STATE <= S2; end if; end if; when S1 => Z3 <= '1'; if (X3 = '0') then NEXT_STATE <= S2; else Z2 <= '1'; NEXT_STATE <= S1; end if; when S2 => if (X4 = '0') then
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