05s_cpe422_midterm_solution

05s_cpe422_midterm_solution - The University of Alabama in...

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The University of Alabama in Huntsville ECE Department CPE/EE 422/522 01 Midterm Exam Solution 1. (10 points) A sequential network consists of a PLA and a D flip-flop, as shown. The propagation delay for the PLA is in the range 5 to 10 ns, and the propagation delay from clock to output of the D flip-flop is 5 to 10 ns. Assuming that X always changes at the same time as the falling edge of the clock, what is the maximum setup and hold time specifications that the flip-flop can have and still maintain proper operation of the network? PLA Clk D Q Z X X 20 40 80 60 100 Q Z For both the setup time and hold time, there are two paths to consider, one from X to the D input of the flip-flop and the other from Q to the D input of the flip-flop. From the timing diagram, tck = 40 ns, tx = 20 ns and ty = 20 ns, where tck is the clock period, tx is the time from a change on X to the active edge of the clock and ty is the time from the active edge of the clock to a change on X. The following equations apply: For Q: (1) t ck t pdmax + t cmax + t su , (2) t h t pdmin + t cmin For X: (3) t x t su + t cmax , (4) t h t y + t cmin where t pd is the propagation delay through the flip-flop and t c is the propagation delay through the combinational circuit (PLA) So, for setup, So, for hold, (1) 40 ns 10 ns + 10 ns + t su , t su 20 ns (2) t h 5 ns + 5 ns, t h 10 ns (3) 20 ns t su + 10 ns , t su 10 ns (4) t h 20 ns + 5 ns, t h 25 ns For both the setup and the hold times to be always satisfied, we must take the smaller numbers so t su = t h = 10 ns 2. (10 points) Write a short VHDL description of a 4-to-1 multiplexer using a VHDL process.
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05s_cpe422_midterm_solution - The University of Alabama in...

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