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ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Assignment #3
Solutions
1. Suppose that a
k
input gate has a delay of
k
seconds, and an area of
k
units. This data is valid for
AND, OR, NAND, NOR gates of any number of inputs, for XOR gates of up to 2 inputs, and for INV
gates.
(a) What is the area and delay of a 12input XOR function, implemented as a minimum SOP?
(b) What is the area and delay of a 12input XOR function, implemented using 2input XOR gates?
Solution.
(a) As we saw in class, the output of an
k
input XOR gate is 1 whenever an odd number
of its inputs are 1. Also, each of its product terms is such that it cannot be combined (using the
combining theorem) with any other product term. Hence the size of the SOP of a XOR gate is
the same as the size of the CSOP for such a gate. A
k
input XOR gate has
2
k

1
product terms.
Therefore a 12 input XOR has
2
11
product terms. This means we need
2
11
AND gates in the
minimum SOP, each with 12 inputs. We also need each variable in its complemented form,
which means we need 12 INV gates. Finally we need a single OR gate with
2
11
inputs.
The total area is therefore (
2
11
* 12) + (12 * 1) + (1 *
2
11
) = 26636.
Assume that all inputs are ready at time 0. All the INV gates produce their outputs at time 1.
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 Fall '09
 wilcox
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