hw5sol - R is high. There is a signal CLK , and whenever...

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ECEN 248: Introduction to Digital System Design Department of Electrical Engineering Assignment #5 Due Thursday, October 22, 2009 1. [15 points.] Consider an output pin of a computer chip A . It is connected to a wire on the printed circuit board. The other end of the wire is connected to the output pin of another chip B . We focus our attention on the circuits that drive the output pins of chip A and chip B (these circuits are called output drivers). (a) Why do the output drivers need to be able to drive a high impedance value? (b) How many input signals would each output driver need? What is the functionality of each of these signals? (c) Write the Verilog code for the output driver of chip A . 2. [15 points.] Consider a gadget that I want to design. The gadget has an input R . A 4-bit counter is reset when
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Unformatted text preview: R is high. There is a signal CLK , and whenever there is a rising edge of CLK , I increment the count (provided R is not low). A final input to the gadget is S , and when this signal is high, the count is frozen. Write the Verilog code for this gadget. 3. [20 points.] Suppose you have a 3-bit adder, implemented in Verilog. The inputs to this adder are X and Y , and the output is Z . Write a testbench which will test the adder exhaustively. In other words, the testbench applies all possible inputs to the adder, and tests that the output from the adder is as expected. If there are no errors, the testbench prints out All tests passed. Otherwise it prints out Error encountered. The testbench does not print out any other information. 1...
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hw5sol - R is high. There is a signal CLK , and whenever...

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