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Unformatted text preview: 2. [30 points.] Consider an 8bit Carry Select Adder (CSA) that we discussed in class. Assume that you can use AND or OR gates (with at most 4 inputs), to implement the carry or sum outputs of the CSA. Assume 1 2 Assignment #6 that INV gates have zero delay and zero area, and assume that the CSA does not have a C input. Assume that a gate with k inputs has a delay of k . (a) What is the minimum number of gates that your CSA needs for each sum and carry output? (b) What is the maximum delay of your CSA? October 23, 2009 Sunil P Khatri ECEN 248...
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This note was uploaded on 06/29/2011 for the course ECEN 248 taught by Professor Wilcox during the Fall '09 term at Texas A&M University, Corpus Christi.
 Fall '09
 wilcox
 Electrical Engineering

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