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# hw6 - 2[30 points Consider an 8-bit Carry Select Adder(CSA...

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ECEN 248: Introduction to Digital System Design Department of Electrical Engineering Texas A&M University Assignment #6 Due Thursday, October 29, 2009 1. [20 points.] Consider the always block below: always @ (posedge CLK) begin a = #4 1; b = #2 1; a = #2 0; end Now consider a second always block below: always @ (posedge CLK) begin a < = #4 1; b < = #2 1; a < = #2 0; end Assume that both always blocks are entered at time 10. The values of a and b are X when we enter each always block. (a) Draw the waveforms of a and b from time 10 onwards, for the first always block. (b) Draw the waveforms of a and b from time 10 onwards, for the second always block.

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Unformatted text preview: 2. [30 points.] Consider an 8-bit Carry Select Adder (CSA) that we discussed in class. Assume that you can use AND or OR gates (with at most 4 inputs), to implement the carry or sum outputs of the CSA. Assume 1 2 Assignment #6 that INV gates have zero delay and zero area, and assume that the CSA does not have a C input. Assume that a gate with k inputs has a delay of k . (a) What is the minimum number of gates that your CSA needs for each sum and carry output? (b) What is the maximum delay of your CSA? October 23, 2009 Sunil P Khatri ECEN 248...
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