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ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Assignment #8
Solutions
1. Consider a function
f
=
ab
+
b
c
.
(a) Write down the recursive Shannon expansion of this function, by using the cofactoring order
a
→
b
→
c
.
(b) Using this as a starting point, implement
f
with the minimum number of MUXes.
(c) Suppose the cofactoring order is changed to
b
→
a
→
c
. Redo the recursive Shannon expan
sion, and from this, find the new implementation of
f
with the minimum number of MUXes.
Solution.
(a) The transformation of the recursive Shannon expansion into a MUXbased circuit
(using a minimum number of MUXes) is shown in Figure 1.
We first transform the recursive Shannon expansion into a MUXbased circuit, by replacing
each nonterminal (i.e. not a ’1’ or ’0’) node by a MUX. Then we minimize the MUX count by
applying two rules:
i. Suppose the variable associated with any node is
x
. Then, if the 0cofactor (call it
f
x
) and
1cofactor (call it
f
x
) of a node
f
are identical, we simply skip that node. This is because,
by SET, we have
f
=
x
·
f
x
+
x
·
f
x
If
f
x
=
f
x
, the above changes to
f
=
x
·
f
x
+
x
·
f
x
=
f
x
Which means that the MUX corresponding to this node can be omitted completely.
ii. We make sure that no two nodes implement the same function (thereby saving on MUXes).
In other words, if any two cofactors in the recursive Shannon expansion tree are identical,
we implement them only once.
The application of these rules is shown in Figure 1.
1
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Solutions to Assignment #8
(b) The transformation of the recursive Shannon expansion into a MUXbased circuit (using a min
imum number of MUXes) is shown in Figure 2. The steps are similar to those outlined in part
(a).
Comment:
Note that we end up using one less MUX than in part (a). This indicates that the
choice of the order in which we cofactor variables influences the minimum size of the MUX
based design.
2. Suppose I have an
n
input XOR function. I want to implement it in two different ways, and compare
the cost of these implementations.
(a) Suppose I implemented it using AND, OR and INVERTER gates. How many gates do I need?
Assume that we can implement AND and OR gates with an arbitrary number of inputs.
(b) Now suppose I implement this function using MUXes and INVERTERs. How many MUXes or
INVERTERs do I need?
Solution.
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 Fall '09
 wilcox
 Electrical Engineering

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