# hw10sol - ECEN 248: Introduction to Digital System Design...

This preview shows pages 1–2. Sign up to view the full content.

Department of Electrical Engineering Assignment #10 Solutions 1. Suppose I want to build a counter which counts from 0 up to 4 (skipping the value 2). When the count reaches 4, my counter then starts counting from 0 to 4 again (always skipping the value 2). In other words, the counter output sequence is 0 1 3 4 0 1 3 4 ··· . The count transitions are made on the rising edge of a CLK signal. Use DFFs for any state elements required by the counter. Assume we want to implement the counter as a Moore machine. Encode the counter states as per the following table: Counter state Encoding 0 00 1 01 3 10 4 11 (a) Can I implement the above with a combinational circuit? If so, state why. If not, state why not. (b) Write down the state transition diagram for the counter. (c) Write down the state transition table from the above. (d) Next write down the minimum SOP for all the NS and output functions. Solution. (a) We cannot implement the above with combinational logic since we have to remember the last value of the counter before we can produce the next value. Hence we need some memory elements and the circuit is sequential. (b) The STG of the counter is shown below. It consists of 4 symbolic states, shown in the figure

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

## hw10sol - ECEN 248: Introduction to Digital System Design...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online