110_1_ANW_2011_ISSCC_preprint

110_1_ANW_2011_ISSCC_preprint - Session_07_Session_...

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24 2011 IEEE International Solid-State Circuits Conference 7.8 A Direct Digital Frequency Synthesizer with Minimized Tuning Latency of 12ns Alan Willson, Mukund Ojha, Shilpa Agarwal, Thriven Lai, Tzu-chieh Kuo University of California, Los Angeles, CA A downside for all direct digital synthesizer (DDS) architectures is that every DDS has a phase accumulator (PA) whose normalized phase value φ must be updated for each (sin 2 πφ , cos 2 πφ ) output-pair produced, and such updating introduces a rather long carry-ripple. PA lengths of 32-b are commonplace and 48-b or longer PA can be found in commercial DDS products. When a DDS with high data-rate is needed, the long PA carry-ripple can present a serious bottle- neck—one usually overcome by some form of PA pipelining—but then, only at the cost of a significant increase in “tuning latency” as well as added power con- sumption and chip-area. Ref. [1] explains how (for a mere 24-b PA) such pipelining introduces a 55-cycle latency, setting the system’s frequency-hopping limit at 700/55 = 12.7MHz, for a DDS generating outputs at 700MHz. All such PA pipelining difficulties are completely eliminated by the architecture reported here. Our new DDS architecture, beyond speeding up PA updating, provides other major benefits, including reduced computation for each DDS output value, hence lower power consumption, and effortlessly providing an increase in DDS output SNR by facilitating the use of carry-ripple-free phase -rounding rather than con- ventional phase truncation. (Note: phase-rounding is not found in any previous DDS architecture.) The Fig. 7.8.1 DDS example has a 32-b PA, split into two 16-b parts. These PA parts get repeatedly updated by simultaneous additions of FCW H and FCW L , the two parts into which the frequency control word (FCW) is split, thus reducing the PA-update carry-ripple bottleneck by half. By using a “single-bit register” to hold the C_out bit for the FCW L addition—with this stored bit becoming a C_in bit for the next FCW H addition—the contents of the upper and lower PA halves ( φ H and φ L ) are always correct, and any desired FCW input change can take effect at an arbitrary instant (a much desired attribute for any DDS) by simultaneously changing FCW H and FCW L and continuing with the PA updates. The issue we must address is to (efficiently—no long carry ripple can be tolerated!) incorpo- rate C_out into the DDS phase-to-amplitude-mapping computations. This is
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This note was uploaded on 07/06/2011 for the course EE 110 taught by Professor Gupta during the Winter '08 term at UCLA.

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110_1_ANW_2011_ISSCC_preprint - Session_07_Session_...

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