buffers_1.3 - Buffering Techniques Greg Stitt ECE...

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Unformatted text preview: Buffering Techniques Greg Stitt ECE Department University of Florida Buffers Purposes Metastability issues Memory clock likely different from circuit clock Buffer stores data at one speed, circuit reads data at another Stores windows of data, delivers to datapath Window is set of inputs needed each cycle by pipelined circuit Generally, more efficient than datapath requesting needed data i.e. Push data into datapath as opposed to pulling data from memory Conversion between memory and datapath widths E.g. Bus is 64-bit, but datapath requires 128-bits every cycle Input to buffer is 64-bit, output from buffer is 128 bits Buffer doesnt say it has data until receiving pairs of inputs FIFOs FIFOs are a common buffer Outputs data in order read from memory + + for (i=0; i < 100; I++) a[i] = b[i] + b[i+1] + b[i+2]; FIFO RAM FIFOs FIFOs are a common buffer Outputs data in order read from memory + + b[0-2] for (i=0; i < 100; I++) a[i] = b[i] + b[i+1] + b[i+2]; RAM b[0] b[1] b[2] First window read from memory FIFO FIFOs are a common buffer Outputs data in order read from memory FIFOs + + b[0-2] for (i=0; i < 100; I++) a[i] = b[i] + b[i+1] + b[i+2]; RAM b[0] b[1] b[2] FIFOs FIFOs are a common buffer Outputs data in order read from memory + + b[1-3] for (i=0; i < 100; I++) a[i] = b[i] + b[i+1] + b[i+2]; RAM b[1] b[2] b[3] b[0] b[1] b[2] First window pushed to datapath Second window read from RAM FIFOs FIFOs are a common buffer Outputs data in order read from memory + + b[2-4] for (i=0; i < 100; I++) a[i] = b[i] + b[i+1] + b[i+2]; RAM b[2] b[3] b[4] b[1] b[2] b[3] b[0]+b[1] b[2] FIFOs Timing issues Memory bandwidth too small Circuit stalls or wastes cycles while waiting for data Memory bandwidth larger than data consumption rate of circuit May happen if area exhausted FIFOs Memory bandwidth too small + + b[0-2] for (i=0; i < 100; I++) a[i] = b[i] + b[i+1] + b[i+2]; RAM b[0] b[1] b[2] First window read from memory into FIFO FIFOs Memory bandwidth too small + + for (i=0; i < 100; I++) a[i] = b[i] + b[i+1] + b[i+2]; RAM b[0] b[1] b[2] b[1-3] 1 st window pushed to datapath 2 nd window requested from memory, but not transferred yet FIFOs Memory bandwidth too small + + for (i=0; i < 100; I++) a[i] = b[i] + b[i+1] + b[i+2]; RAM b[1-3] No data ready (wasted cycles) 2 nd window requested from memory, but not transferred yet b[0]+b[1] b[2] Alternatively, could have prevented 1 st window from proceeding (stall cycles) - necessary if feedback in pipeline FIFOs...
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buffers_1.3 - Buffering Techniques Greg Stitt ECE...

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