DATE09_jara-berrocal_SCORES - SCORES A Scalable and...

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SCORES: A Scalable and Parametric Streams-Based Communication Architecture for Modular Reconfigurable Systems Abelardo Jara-Berrocal and Ann Gordon-Ross NSF Center for High-Performance Reconfigurable Computing (CHREC) ECE Department, University of Florida, Gainesville, FL 32611 {berrocal, [email protected] Abstract - Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applications are decomposed into multiple computational modules (tasks) that collectively operate and communicate in parallel. In this paper, we present a scalable and highly parametric streams-based communication architecture for inter-module communication for FPGA-based systems SCORES. This communication architecture improves on previous methods by providing increased application specialization and heterogeneous module clock frequencies, as well as providing a means for low latency communication and data throughput guarantees. I. INTRODUCTION AND MOTIVATION One of the most important design considerations in VLSI digital systems is achieving high performance with low power consumption. Parallel architectures provide a popular method in which to achieve these goals [6]. Parallel architectures enable application decomposition into multiple computing modules, operating and communicating in parallel and which collectively encompass entire application behavior. In order to exploit potential speedup as the number of modules increases, an efficient communication architecture to support inter-module communication is required. Traditional bus-based communication architectures enable all computing modules to communicate over a common shared bus, providing great flexibility for varying levels of inter-module communication requirements. However, bus-based communication architectures scale poorly as the number of computing modules increases [5]. This poor scalability results from shared transmission media contention and long routing wire delays, of which collectively imply long routing delays, reduced maximum clock frequency, and reduced throughput. In order to alleviate some of the bus-based communication architecture drawbacks, a Network-on-Chip (NoC) architecture was proposed as a paradigm for scalable and parallel communication architectures [3]. NoCs are constructed as a topology of networked nodes connected by physical communication links. Each computing module is attached to this topology via a networked node. Depending on the communication scheme used, networked nodes can be classified as routers (packet switching) or switches (circuit switching). NoCs appear to be a good alternative to bus-based communication. Network nodes provide breaks in the long routing wires inherent in a bus-based architecture, and therefore typically achieve higher operating frequencies. Furthermore, the main advantage of a NoC is scalability and specialization
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This note was uploaded on 07/25/2011 for the course EEL 4930 taught by Professor Staff during the Fall '08 term at University of Florida.

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DATE09_jara-berrocal_SCORES - SCORES A Scalable and...

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