ERSA08_conger_PR - 1 Design Framework for Partial Run-Time...

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Unformatted text preview: 1 Design Framework for Partial Run-Time FPGA Reconfiguration Chris Conger, Ann Gordon-Ross, and Alan D. George NSF Center for High-Performance Reconfigurable Computing (CHREC) ECE Department, University of Florida, Gainesville, Florida 32611 Email: {conger, ann, [email protected] Abstract Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increased functionality. Even though recent advances in Xilinx’s Virtex-4 and Virtex-5 FPGA devices and design tools significantly improve the practicality of incorporating PR, unfortunately, system designers largely lack sufficient guidance to design these systems. Efficient system design exploration and extensive manual floorplanning is required to fully enhance the capabilities of a system and/or optimize metrics such as power consumption, device quantity and size, designer productivity, and design re-use. To fully leverage PR, system designers must acquire a strong knowledge of the PR design flow as well as the low-level architectural details of their target device. In this paper, we propose design methodologies to assist designers in efficient PR system design and define frameworks to enable rapid system prototyping, enabling designers to harness the capabilities of PR without having to deal with many of the intricate details. Furthermore, we identify new opportunities for optimization, which are only made possible with the tile-based layout of the Virtex-4 and Virtex-5 FPGAs. 1. Introduction SRAM-based FPGAs are reprogrammable hardware devices that enable modification to their hardware architecture easily and dynamically during runtime. Whereas this reconfiguration allows changes to functionality, one potential drawback is that even small changes require updating the entire FPGA fabric, potentially disrupting system execution, as the entire system may need to stall during reconfiguration and system reset. Given the increasing size of FPGA fabrics, this reconfiguration time can be prohibitive as bitstream sizes (data needed to reconfigure the fabric) increase. Furthermore, if many different FPGA configurations are required, a prohibitive amount of memory may be needed to store all the bitstreams. Dynamic partial reconfiguration (PR) enhances FPGA systems by partitioning the fabric into numerous reconfigurable regions, and allowing these regions to be independently reconfigured during runtime. By reconfiguring only the region of the fabric that requires modification, the remainder of the fabric (the regions not being reconfigured) continues execution without disruption. Since PR regions may be much smaller than the entire fabric, PR can result in reductions in reconfiguration time, bitstream communication, and storage memory....
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This note was uploaded on 07/25/2011 for the course EEL 4930 taught by Professor Staff during the Fall '08 term at University of Florida.

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ERSA08_conger_PR - 1 Design Framework for Partial Run-Time...

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