F4_Presentation_RC_Class_Fall09

F4_Presentation_RC_Class_Fall09 - 2009 Midyear Workshop...

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Unformatted text preview: 2009 Midyear Workshop F4-09: Virtual Architecture and Design F4-09: Virtual Architecture and Design Automation for Partial Reconfiguration Automation for Partial Reconfiguration All Hands Meeting November 10th, 2009 Dr. Ann Gordon-Ross Assistant Professor of ECE University of Florida Dr. Alan D. George Professor of ECE University of Florida Abelardo Jara Terence Frederick Rohit Kumar Shaon Yousuf Research Students University of Florida Outline Goals, Motivation and Challenges Virtual Architecture for Partially Reconfigurable Embedded System (VAPRES) Design methodology Multiple clock domains support Bitstream relocation MACS Inter-module Communication Architecture Case Study Application: Embedded Target Tracking System on Virtex-4 FPGA board Preliminary non-PR version using Kalman filters Design Automation for Partial Reconfiguration (DAPR) DAPR design flow VHDL annotations Connectivity file and graph Device library file Overlay generation 3 GOAL Leverage partial reconfiguration (PR) for application designers Architect and implement a Virtual Architecture (VA) for Partially Reconfigurable Embedded Systems Ease PR design via design automation MOTIVATIONS Increase productivity and reduce design complexity for PR designs VA reduces development time Dynamically load and unload hardware processing modules Processing hardware adapts to external environmental conditions Automated design flow makes PR more amenable system designers Current PR design flow requires very high level of specialization Simplifies design of systems that time-multiplex FPGA resources smaller devices CHALLENGES Provide sufficient VA flexibility with architectural parameterization Balancing enough application specialization with exploration complexity Creating new exploration algorithms/heuristics to automate PR design flow steps with respect to available PR tools 3 3 Goals, Motivations, and Challenges Goals, Motivations, and Challenges Sensor Interface Central Controlling Agent ICAP Processed output Filter repository Filter A Filter B PRR Filter A External Trigger Sensor Coverage Area 4 Expand and prototype an FPGA-based architecture for rapid development of PR embedded systems VAPRES: Virtual Architecture for Partially Reconfigurable Embedded Systems MACS: Minimal Adaptive Circuit Switching mesh inter-module communication architecture for VAPRES Improvement over F4-08 SCORES communication architecture Architectural support for hardware module context save and restore Formulate and implement an automated PR design flow DAPR: Design Automation for Partial Reconfiguration Tool Study Virtex-4 and Virtex-5 bitstreams to leverage additional functionalities Extend bitstream relocation and context save and restore for Virtex-5 F4-09 Approach F4-09 Approach Highly specialized PR system design Reconfiguration...
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This note was uploaded on 07/25/2011 for the course EEL 4930 taught by Professor Staff during the Fall '08 term at University of Florida.

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F4_Presentation_RC_Class_Fall09 - 2009 Midyear Workshop...

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