rt_synth_1.2 - Register-Transfer (RT) Synthesis Greg Stitt...

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Register-Transfer (RT) Synthesis Greg Stitt ECE Department University of Florida
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Introduction Register-transfer (RT) synthesis Definition: Synthesis from register transfer level (RTL) descriptions VHDL, Verilog typically describe circuits as connections of RTL components What are register-transfer level components? Muxes, ALUs, registers, multipliers, etc. One abstraction level above gates Basically, components you use in most structural descriptions What are other levels? Transistor level Gate level Register transfer level High level System level Etc.
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RT Synthesis Main Steps Lex/Parsing Analyzes HDL, converts into intermediate representation Resource Allocation Maps intermediate representation into RT components Optimizations Logic minimization State minimization State encoding Etc. Technology Mapping Placement + Routing
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Technology Mapping Converts circuit from one technology (e.g. gates) onto technology used by physical device (e.g. LUTs, CLBs, etc) CLB CLB CLB CLB CLB CLB
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Placement Input: Technology-mapped circuit For simplicity, just consider CLBs Technology-mapped circuit consists of “virtual” CLBs and “virtual” connections FPGA fabric consists of physical CLBs Simplified Placement Definition: Map “virtual” CLBs onto physical CLBs I.e. Decide on a location in the FPGA for each virtual CLB 1 2 3 4 6 5 CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB 1 2 3 4 CLB 5 CLB 6 CLB CLB CLB CLB CLB CLB CLB Technology Mapped Circuit FPGA Fabric Possible Placement
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Routing Input: A set of placed components, and a list of “virtual” connections Simplified Routing Definition: Determine how to configure routing resources to implement “virtual” connections 1 2 3 4 CLB 5 CLB 6 CLB CLB CLB CLB CLB CLB CLB 1 2 3 4 6 5 Physical CLBs not connected – must configure routing these connections:
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Placement+Routing (PAR) Placement and routing highly dependent Placement affects how well circuit can be routed Example: 1 2 3 4 6 5 1 2 3 4 CLB 5 CLB 6 CLB CLB CLB CLB CLB CLB CLB 6 3 CLB 1 CLB CLB CLB 4 CLB CLB 2 CLB CLB CLB 5 Placement 1 Placement 2 Clearly, placement 1 is easier to route
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Placement+Routing (PAR) Goals: 1) Make sure circuit can be implemented on fabric Trivial for placement, difficult for routing Bad placement may make circuit unroutable 2) Minimize delay of critical path Critical path is the longest register to register delay Important - Determines clock speed of circuit Why is placement and routing important?
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rt_synth_1.2 - Register-Transfer (RT) Synthesis Greg Stitt...

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