SHMEM_aggarwal - Bridging Parallel and Reconfigurable...

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Bridging Parallel and Reconfigurable Computing with Multilevel PGAS and SHMEM+ V. Aggarwal, A. George, K. Yalamanchili, C. Yoon, H. Lam, G. Stitt NSF Center for High-Performance Reconfigurable Computing (CHREC) ECE Department, University of Florida, Gainesville, FL 32611-6200 {aggarwal, george, yalamanchili, yoon, hlam, [email protected] ABSTRACT Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such systems have demonstrated superior performance and reduced energy consumption versus their traditional counterparts based on microprocessors. However, most of such work has been limited to small system sizes. Unlike traditional HPC systems, lack of integrated, system-wide, parallel-programming models and languages presents a significant design challenge for creating applications targeting scalable, reconfigurable HPC systems. In this paper, we introduce and investigate a novel programming model based on Partitioned Global Address Space (PGAS), which simplifies development of parallel applications for such systems. The new multilevel PGAS programming model captures the unique characteristics of these systems, such as the existence of multiple levels of memory hierarchy and heterogeneous computation resources. To evaluate this multilevel PGAS model, we extend and adapt the SHMEM programming language to become what we call SHMEM+, the first known SHMEM library enabling coordination between FPGAs and CPUs in a reconfigurable, heterogeneous HPC system. Our design of SHMEM+ is highly portable and provides peak communication bandwidth comparable to vendor-proprietary versions of SHMEM. In addition, applications designed with SHMEM+ yield improved developer productivity compared to current methods of multi-device RC design and achieve a high degree of portability. Categories and Subject Descriptors D.1.3 [ Programming Techniques ]: Concurrent Programming – parallel programming. General Terms Design, Languages, Performance Keywords Reconfigurable computing, parallel programming, programming language, programming model, productivity, portability. 1. INTRODUCTION High-performance computing (HPC) is a critical enabling technology for the advancement of science and engineering, supporting multi-scale simulations and experiments that drive breakthroughs in an ever-broadening range of fields. The field of HPC is currently undergoing a major transformation brought on by advances in device technologies as well as new generations of fixed-logic [1][2][3], reconfigurable-logic [4][5], and/or heterogeneous multicore and many-core [2][6][7] devices. These technologies are driving systems to become ever more powerful and efficient but unfortunately also more complex and demanding, with multiple types and levels of hardware parallelism to be understood and exploited. A
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This note was uploaded on 07/25/2011 for the course EEL 4930 taught by Professor Staff during the Fall '08 term at University of Florida.

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SHMEM_aggarwal - Bridging Parallel and Reconfigurable...

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