CMOS compatible contacts and etching for InP-on-silicon active devices

CMOS compatible contacts and etching for InP-on-silicon active devices

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Unformatted text preview: CMOS compatible contacts and etching for InP-on-silicon active devices L. Grenouillet 1 , A.L. Bavencove 1 , T. Dupont 1 , J. Harduin 1 , P. Philippe 1 , P. Regreny 2 , F. Lelarge 3 , K. Gilbert 1 , P. Grosse 1 , and J.M. Fedeli 1 . 1 CEA-LETI-Minatec, 17 rue des Martyrs, 38054 Grenoble, France. 2 Institut des Nanotechnologies de Lyon, INL, UMR 5270, Ecole Centrale de Lyon, 36, avenue Guy de Collongue, Ecully, France 3 Alcatel-Thales III-V lab, Route de Nozay, 91460 Marcoussis, France. [email protected] Abstract — We present CMOS compatible dry etching and nonalloyed ohmic contacts on InP dice on silicon. These developments are validated through the demonstration of a continuous wave III-V/Si laser with etched facets and gold free contacts. I. INTRODUCTION The field of silicon photonics aims at merging photonics devices on CMOS circuits with microelectronics tools on large size wafers. This full integration enables either improved functionality of the electronic circuits or miniaturization of optical functions. Even though most of the required optical functions (routing, multiplexing, demultiplexing, coupling, modulation, photodetection, actuation) can be realized with silicon or silicon related materials, up to now only InP-based III-V materials allowed for the realization of compact and efficient laser sources on silicon [1,2]. A promising approach to merge microelectronics and optoelectronics on a CMOS platform for including the laser sources therefore necessitates to make use of heterogeneous integration by means of die-to-wafer molecular bonding [3] using the so-called above IC approach. In this approach, the optical active devices are fabricated at the back-end levels and the temperature budget is limited to 400°C. Even though SiO 2 /SiO 2 molecular bonding of InP dice on 200mm Si wafers was already reported [3], still some problems remain for the III-V/Si processing. Firstly, dry etching processes of InP dice bonded on silicon need to be developed at the 200mm scale without impacting the silicon or silicon dioxide materials. This is mandatory as there are large wafer areas free of InP material that are exposed to the plasma. Secondly, to our knowledge only III-V on silicon lasers processed in optoelectronics clean room with gold- based contacts obtained by lift off were reported. These kinds of contacts are not CMOS compatible. Indeed gold acts as a deep level in silicon and is therefore strictly forbidden in a microelectronics room. Moreover, the lift off process is not well known in the field of microelectronics where usually thin photoresist layers are used. In this paper we present recent developments that pave the way to a full integration of InP on silicon in CMOS pilot lines....
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CMOS compatible contacts and etching for InP-on-silicon active devices

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