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Unformatted text preview: A Survey of Processors with Explicit Multithreading THEO UNGERER University of Augsburg BORUT ROBI ˇ C University of Ljubljana AND JURIJ ˇ SILC Joˇzef Stefan Institute Hardware multithreading is becoming a generally applied technique in the next generation of microprocessors. Several multithreaded processors are announced by industry or already into production in the areas of high-performance microprocessors, media, and network processors. A multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline. The contexts of two or more threads of control are often stored in separate on-chip register sets. Unused instruction slots, which arise from latencies during the pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor. The execution units are multiplexed between the thread contexts that are loaded in the register sets. Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple threads each cycle. Simultaneous multithreaded processors combine the multithreading technique with a wide-issue superscalar processor to utilize a larger part of the issue bandwidth by issuing instructions from different threads simultaneously. Explicit multithreaded processors are multithreaded processors that apply processes or operating system threads in their hardware thread slots. These processors optimize the throughput of multiprogramming workloads rather than single-thread performance. We distinguish these processors from implicit multithreaded processors Categories and Subject Descriptors: C.1 [ Computer Systems Organization ]: Processor Architectures; C.1.3 [ Processor Architectures ]: Other Architecture Styles— Pipeline processors General Terms: Design, Performance Additional Key Words and Phrases: Blocked multithreading, interleaved multithreading, simultaneous multithreading Authors’ addresses: T. Ungerer, Institute of Computer Science, University of Augsburg, Eichleitnerstrasse 30, D-86135 Augsburg, Germany; email: [email protected]; B. Robiˇc, Faculty of Com- puter and Information Science, University of Ljubljana, Trˇzaˇska 25, Sl-1000 Ljubljana, Slovenia; email: [email protected]; J. ˇ Silc, Computer Systems Department, Joˇzef Stefan Institute, Jamova 39, Sl-1000 Ljubljana, Slovenia; email: [email protected] Permission to make digital/hard copy of part or all of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication, and its date appear, and notice is given that copying is by permission of the ACM, Inc. To copy otherwise, to republish, to post on servers, or to redistribute to listspermission of the ACM, Inc....
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- Spring '11
- Computer Science, Central processing unit, processor, Context switch, ACM Computing Surveys, THEO UNGERER