active_lowpower - An ASIC Low Power Primer Rakesh Chadha \u2022 J Bhasker An ASIC Low Power Primer Analysis Techniques and Specification Rakesh Chadha

active_lowpower - An ASIC Low Power Primer Rakesh...

This preview shows page 1 out of 225 pages.

Unformatted text preview: An ASIC Low Power Primer Rakesh Chadha • J. Bhasker An ASIC Low Power Primer Analysis, Techniques and Specification Rakesh Chadha eSilicon Corporation New Providence, NJ, USA J. Bhasker eSilicon Corporation Allentown, PA, USA ISBN 978-1-4614-4270-7 ISBN 978-1-4614-4271-4 (eBook) DOI 10.1007/978-1-4614-4271-4 Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2012950049 © Springer Science+Business Media New York 2013 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media ( ) Preface How many times have you been ready to take a picture or a video when the battery in your device runs out? Invariably, it frequently happens to many of us. Even though the problem is not the lack of power in the battery, or conversely, that the unit has consumed too much power, guess who gets the brunt of the anger? In such moments, we always wish the camera or the video recorder did not consume so much power. However, it could be that, even in standby mode, the device was consuming a lot of power without our knowledge. Most of us are now aware of the importance of power. From the giant server farms that consume large amounts of power to the smallest portable units such as a pacemaker that needs to last for a long time, the power requirement is a critical item of interest. For the giant server farms, they want to go “green,” consume less power so that the operating costs as well as the impact on the environment are minimized. For the smallest portable units such as a pacemaker, you want the unit to last forever. The key to achieving all of these is to understand and analyze where the power is being consumed, have a way to measure the power, and finally adopt techniques that can reduce the amount of power consumed by the device or system. In this book, we focus primarily on the CMOS digital ASIC devices. The book explores the three paradigms, how to analyze or measure power, how to specify the power intent for a device, and what techniques can be used to minimize the power consumption. One of the challenges in measuring the power of an ASIC device is to figure out the conditions for worst-case power consumption. Is the power larger in cold conditions or in hot conditions? Is it when you press button A and button B together or is it when you press button A and button C together? Is the power worse while browsing the Internet, or is it worse when playing a video game? Is the power in standby mode also a large value? These questions indicate that there is a concept of the worst power scenario. It is likely that a user may never operate under such a scenario. So do you really need to design the device to handle such conditions? Or should you target the power to be minimized for typical applications? An ASIC system designer has his or her work cut out, as these are not easy questions to answer. For example, an MP3 player was not power-optimized for playing video songs. If it plays only v vi Preface audio songs, the battery lasts for 4 days. If it plays video songs, the battery runs out within 6 h. This book is targeted towards professionals working on ASIC designs. A background in logic design is required. It has been written in an easy-to-read style where there are almost no dependencies amongst the chapters. You can jump into the chapter of interest straightaway. Initial chapters are focused on explaining how to measure power. Later chapters describe the implementation strategies to reduce power, and finally, we describe the languages that can be used to describe the power intent. Acknowledgments We would like to express our deep gratitude to eSilicon Corporation for providing us the opportunity to write this book. We also would like to thank and acknowledge the valuable feedback provided by Marc Galceran-Oms, Pete Jarvis, Luke Lang, Carlos Macian, Ferran Martorell, Satya Pullela, Prasan Shanbag, Hormoz Yaghutiel, and Per Zander. Their feedback has been invaluable. Last but not least, we would like to thank our families for their patience during the development of this book. New Providence, NJ, USA Allentown, PA, USA Rakesh Chadha J. Bhasker vii Contents 1 Introduction .............................................................................................. 1.1 What Is Power? ................................................................................. 1.2 Why Is Power Important? ................................................................. 1.3 Why Is Power Increasing?................................................................. 1.4 Where Is the Power Going? .............................................................. 1.5 How Much Is Low? ........................................................................... 1.6 Why Measure? .................................................................................. 1.7 Impact on Design Complexity .......................................................... 1.8 Outline of the Book ........................................................................... 1 1 1 2 3 4 5 6 7 2 Modeling of Power in Core Logic ........................................................... 2.1 Power Dissipation in Digital Designs ............................................... 2.1.1 Example Using Ideal Switch ................................................. 2.1.2 CMOS Digital Logic ............................................................. 2.2 Dynamic or Active Power ................................................................. 2.2.1 Active Power in Combinational Cells ................................... 2.2.2 Active Power in Sequential Cells .......................................... 2.2.3 Internal Power Dependence of Parameters ........................... 2.3 Leakage Power .................................................................................. 2.3.1 Dependence on Threshold Voltage........................................ 2.3.2 Dependence on Channel Length ........................................... 2.3.3 Dependence on Temperature ................................................. 2.3.4 Dependence on Process ......................................................... 2.3.5 Modeling of Leakage Power ................................................. 2.4 Advanced Power Modeling ............................................................... 2.4.1 Leakage Current .................................................................... 2.4.2 Dynamic Current ................................................................... 2.5 Summary ........................................................................................... 9 9 9 10 14 15 18 20 20 21 21 22 22 23 23 24 24 26 ix x Contents 3 Modeling of Power in IOs and Macro Blocks........................................ 3.1 Memory Macros ................................................................................ 3.1.1 Dynamic or Active Power ..................................................... 3.1.2 Leakage Power ...................................................................... 3.2 Power Dissipation in Analog Macros................................................ 3.3 Power Dissipation in IO Buffers ....................................................... 3.3.1 General Purpose Digital IOs ................................................. 3.3.2 High Speed IOs with Termination......................................... 3.4 Summary ........................................................................................... 27 27 28 31 33 34 34 40 43 4 Power Analysis in ASICs ......................................................................... 4.1 What Is Switching Activity? ............................................................. 4.1.1 Static Probability ................................................................... 4.1.2 Transition Rate ...................................................................... 4.1.3 Examples ............................................................................... 4.2 Power Computation for Basic Cells and Macros .............................. 4.2.1 Power Computation for a 2-Input NAND Cell ..................... 4.2.2 Power Computation for a Flip-Flop Cell............................... 4.2.3 Power Computation for a Memory Macro ............................ 4.3 Specifying Activity at the Block or Chip Level ................................ 4.3.1 Default Global Activity or Vectorless ................................... 4.3.2 Propagating Activity from Inputs.......................................... 4.3.3 VCD ...................................................................................... 4.3.4 SAIF ...................................................................................... 4.4 Power Analysis at Chip Level ........................................................... 4.4.1 Selecting the PVT Corner ..................................................... 4.4.2 Power Analysis...................................................................... 4.5 Summary ........................................................................................... 45 45 45 46 46 46 47 53 55 58 58 58 59 61 63 63 64 65 5 Design Intent for Power Management ................................................... 5.1 Power Management Requirements.................................................... 5.2 Power Domains ................................................................................. 5.2.1 Power Domain States ............................................................ 5.3 Special Cells for Power Management ............................................... 5.3.1 Isolation Cells........................................................................ 5.3.2 Level Shifters ........................................................................ 5.3.3 Enable Level Shifters ............................................................ 5.3.4 Power Switches ..................................................................... 5.3.5 Always-on Cells .................................................................... 5.3.6 Retention Cells ...................................................................... 5.3.7 Clock Gate Cells ................................................................... 5.3.8 Standard Cells ....................................................................... 5.3.9 Dual Rail Memories .............................................................. 5.4 Summary ........................................................................................... 67 67 67 69 70 70 72 75 76 80 82 85 88 90 91 Contents xi 6 Architectural Techniques for Low Power .............................................. 6.1 Overall Objectives ........................................................................... 6.1.1 Parameters Affecting Power Dissipation ............................ 6.2 Variable Frequency.......................................................................... 6.3 Dynamic Voltage Scaling ................................................................ 6.4 Dynamic Voltage and Frequency Scaling ....................................... 6.5 Reducing VDD ................................................................................ 6.6 Architectural Clock Gating ............................................................. 6.7 Power Gating ................................................................................... 6.7.1 State Retention .................................................................... 6.7.2 Coarse-Grain and Fine-Grain Power Gating ....................... 6.8 Multi-voltage ................................................................................... 6.8.1 Optimizing Level Shifters ................................................... 6.8.2 Optimizing Isolation Cells .................................................. 6.9 Optimizing Memory Power............................................................. 6.9.1 Grouping the Memory Accesses ......................................... 6.9.2 Avoiding Redundant Activity on Enable Pins ..................... 6.10 Operand Isolation ............................................................................ 6.11 Operating Modes of Design ............................................................ 6.12 RTL Techniques .............................................................................. 6.12.1 Minimizing Transitions ..................................................... 6.12.2 Resource Sharing .............................................................. 6.12.3 Others ................................................................................ 6.13 Summary ......................................................................................... 93 93 94 95 95 97 98 98 99 100 102 103 104 105 106 106 107 107 109 110 110 110 111 111 7 Low Power Implementation Techniques ................................................ 7.1 Technology Node and Library Trade-Offs ...................................... 7.2 Library Selection ............................................................................. 7.2.1 Multi-Vt Cells ..................................................................... 7.2.2 Multi-channel Cells ............................................................. 7.3 Clock Gating ................................................................................... 7.3.1 Power-Driven Clock Gating ................................................ 7.3.2 Other Techniques to Reduce Clock Tree Power.................. 7.4 Timing Impact Due to Clock Gating ............................................... 7.4.1 Single Stage Clock Gating .................................................. 7.4.2 Multiple Stage Clock Gating............................................... 7.4.3 Cloning Clock Gates ........................................................... 7.4.4 Merging ............................................................................... 7.5 Gate-Level Power Optimization Techniques................................... 7.5.1 Using Complex Cells .......................................................... 7.5.2 Cell Sizing ........................................................................... 7.5.3 Appropriate Slew Target for Design ................................... 7.5.4 Pin Swapping ...................................................................... 7.5.5 Factoring ............................................................................. 113 113 114 114 115 116 118 119 120 120 122 123 124 125 125 125 126 126 126 xii Contents 7.6 Power Optimization for Sleep Modes ............................................. 7.6.1 Back Bias for Leakage Reduction ..................................... 7.6.2 Switching OFF Inactive Blocks ........................................ 7.6.3 Sleep and Shutdown Modes for Memories ....................... Adaptive Process Monitor ............................................................... Decoupling Capacitances and Leakage........................................... Summary ......................................................................................... 127 127 129 132 135 136 138 8 UPF Power Specification ......................................................................... 8.1 Setting Scope................................................................................... 8.2 Creating Power Domains ................................................................ 8.3 Creating Supply Ports ..................................................................... 8.4 Creating Supply Nets ...................................................................... 8.5 Connecting Supply Nets.................................................................. 8.6 Primary Supplies of a Domain ........................................................ 8.7 Creating a Power Switch ................................................................. 8.8 Mapping the Power Switch ............................................................. 8.9 State to Supply Port......................................................................... 8.10 Power State Table ............................................................................ 8.11 Level Shifter Specification .............................................................. 8.12 Isolation Strategy ............................................................................ 8.13 Retention Strategy ........................................................................... 8.14 Mapping the Retention Registers .................................................... 8.15 Mychip Example ............................................................................. 139 139 139 141 142 142 142 143 144 144 144 146 147 148 149 150 9 CPF Power Specification ......................................................................... 9.1 Introduction ..................................................................................... 9.2 Library Commands.......................................................................... 9.2.1 Define Always-on Cell ...................................................... 9.2.2 Define Global Cell............................................................. 9.2.3 Define Isolation Cell ......................................................... 9.2.4 Define Level Shifter Cell................................................... 9.2.5 Define Open Source Input Pin........................................... 9.2.6 Define Pad Cell ................................................................. 9.2.7 Define Power Clamp Cell.................................................. 9.2.8 Define Power Clamp Pins ................................................. 9.2.9 Define Power Switch Cell ................................................. 9.2.10 Define Related Power Pin ................................................. 9.2.11 Define State Retention Cell ............................................... 9.3 Power Mode Commands ................................................................. 9.3.1 Create Mode ...................................................................... 9.3.2 Create Power Mode ........................................................... 9.3.3 Specify Power Mode ...
View Full Document

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture