Lecture26 - Click to edit Master subtitle style 8/1/11...

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Unformatted text preview: Click to edit Master subtitle style 8/1/11 Lecture 26 COT 4600 Operating Systems Fall 2009 Dan C. Marinescu Office: HEC 304 Office hours: Tu-Th 3:00-4:00 PM Lecture 26 8/1/11 Lecture 26 - Thursday November 18, 2010 Final exam Thursday December 9 4-6:50 PM n Last time: Scheduling Scheduling algorithms n Today: Multi-level memories Memory characterization Multilevel memories management using virtual memory Adding multi-level memory management to virtual memory n Next Time: Page replacement algorithms Lecture 26 22 Lecture 26 8/1/11 Lecture 26 33 Lecture 26 8/1/11 Lecture 26 44 Lecture 26 8/1/11 The modular design n VM attempts to translate the virtual memory address to a physical memory address n If the page is not in main memory VM generates a page-fault exception . n The exception handler uses a SEND to send to an MLMM port the page number n The SEND invokes ADVANCE which wakes up a thread of MLMM n The MMLM invokes AWAIT on behalf of the thread interrupted due to the page fault. n The AWAIT releases the processor to the SCHEDULER thread. Lecture 26 55 Lecture 26 8/1/11 A p p lica tio n th re a d 1 V irtu a l M e m o ry M a n a g e r E xce p tio n H a n d le r S ch e d u le r M u lti-L e ve l M e m o ry M a n a g e r A p p lica tio n th re a d 2 IR P C T ra n sla te (P C ) in to (P a g e # ,D isp l) Is (P a g e# ) in p rim a ry sto ra g e ? Y E S- co m p u te th e p h ysica l a d d re ss o f th e in stru ctio n IR P C N O p a g e fa u lt S a ve P C H a n d le p a g e fa u lt Id e n tify P a g e # Issu e A W A IT o n b e h a lf o f th re a d 1 A W A IT S E N D (P a g e # ) T h re a d 1 W A IT IN G T h re a d 2 R U N N IN G IR P C L o a d P C o f th re a d 2 F in d a b lo ck in p rim a ry sto ra g e Is d irty b it o f b lo ck O N ? Y E S- w rite b lo ck to se co n d a ry sto ra g e N O - fe tch b lo ck co rre sp o n d in g to m issin g p a g e I/O o p e ra tio n co m p le ts A D V A N C E T h re a d 1 R U N N IN G L o a d P C o f th re a d 1 IR P C Lecture 26 66 Lecture 26 8/1/11 Name resolution in multi- level memories n We consider pairs of layers: Upper level of the pair G primary Lower level of the pair - secondary n The top level managed by the application which generates LOAD and STORE instructions to/from CPU registers from/to named memory locations n The processor issues READs/WRITEs to named memory locations. The name goes to the primary memory device located on the same chip as the processor which searches the name space of the on-chip cache (L1 cache), the primary device with the L2 cache as secondary device. n If the name is not found in L1 cache name space the Multi-Level Memory Manager (MLMM) looks at the L2 cache (off-chip cache) which becomes the primary with the main memory as secondary....
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This note was uploaded on 07/30/2011 for the course COP 4600 taught by Professor Montagne during the Spring '08 term at University of Central Florida.

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Lecture26 - Click to edit Master subtitle style 8/1/11...

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