note8 - Handout 8 CMOS Digital Circuits What you will...

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Handout 8 ECE 315, Cornell University 1 CMOS Digital Circuits What you will learn: • Voltage transfer curve (VTC), switching threshold and noise margins as a function of ( W/L ) NMOS to ( W/L ) PMOS . • Full complementary logic and transistor sizing • Ratioed logic (pseudo-NMOS) and transistor sizing • Pass transistor logic and transistor sizing • Dynamic and domino logic • Static memory based on the positive feedback and the write/erase/read operations • Pseudo-static memory and dynamic memory Handout 8
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Handout 8 ECE 315, Cornell University 2 • Pullup and pulldown network with load lines • Voltage transfer curves: definition of switching threshold and noise margin W/L for NMOS and PMOS and the influence on VTC • Digital circuits are most often large signal and broadband in contrast to analog • Definition of delay and power consumption Textbook: Chap. 4.10; 10.1 – 10.2 8.1 CMOS Inverter Characteristics
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Handout 8 ECE 315, Cornell University 3 Overview of Logic Families Logic Circuit Families CMOS Bipolar BiCMOS GaAs Full Compl. CMOS Pseudo NMOS Pass Trans. Logic Dynamic Logic TTL ECL Fully Compl. Fig. 10.1
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Handout 8 ECE 315, Cornell University 4 Digital Logic Network Pull-up Network (PUN) Pull-down Network (PDN) V DD A B A B C L • In MOS-based digital logic, the signal is fed into the gates of MOSFET, which is mostly capacitive (so the load is often C L ). • PMOS passes strong 1 (pullup) and NMOS passes strong zero (pulldown). • Logic can be implemented in PUN or PDN (the other then needs to be with proper resistive load) or in both (signal to both PUN and PDN) The highest intended voltage is V DD , and the lowest is ground. Load C L charged through PUN. Load C L discharged through PDN.
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Handout 8 ECE 315, Cornell University 5 PUN and PDN and Load Lines PUN PDN V DD V I V I C L • The load lines can be used to construct the VTC. • The load C L in quasi-static operations is an open circuit. V O I V O for PDN V DD V O for PUN I V DD PDN: NMOS different V I values For each V I , you can find the corresponding V O and I as the quasi-static operational points. PUN: resistor Give V O and I for each V I Fig. 10.8
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Handout 8 ECE 315, Cornell University 6 CMOS Inverter as PUN and PDN S D G S D G ( L/W ) PMOS ( L/W ) NMOS close at “0” open at “1” close at “1” open at “0” The output level of v O is independent of W/L : ratioless logic complementary switching!!! I discharge Charging: PUN Discharging: PDN Fig. 4.54 Fig. 10.4 v O v O v I I charge I discharge I charge
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Handout 8 ECE 315, Cornell University 7 PMOS PMOS NMOS NMOS Pullup Pulldown ( W/L ) PMOS ( W/L ) NMOS ( W/L ) PMOS ( W/L ) NMOS Fig. A.12
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Handout 8 ECE 315, Cornell University 8 CMOS Inverter Load Lines V DD V O for PMOS I V DD V DD V I C L V O I Quasi- static V O for NMOS V I =5V V I =4V V I =3V V I =2V V I =1V V I =0V V I =0V V I =1V V I =2V V I =3V V I =4V V I =5V k p W p /L p = k n W n /L n here
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Handout 8 ECE 315, Cornell University 9 CMOS Inverter Operating Regions V I =V O V I V O NMOS off PMOS linear NMOS sat PMOS linear NMOS sat PMOS sat NMOS linear PMOS sat NMOS linear
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This note was uploaded on 02/02/2008 for the course ECE 3150 taught by Professor Spencer during the Fall '07 term at Cornell University (Engineering School).

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note8 - Handout 8 CMOS Digital Circuits What you will...

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