CSC258 Computer Organization 2010 winter Assignment 2 due Mon.Mar.1 at 5pm in BA2220 1 Design a circuit with 7 bits of input p 1 p 2 d 3 p 4 d 5 d 6 d 7 and 7 bits of output q 1 q 2 x 3 q 4 x 5 x 6 x 7 . The output is the same as the input except corrected according to the single error correcting Hamming code. 2 A serial two's complement negater is a sequential circuit with inputs x and y and clock c , and output z . When a two's complement number is presented on input x , one bit per clock cycle, least significant (rightmost) bit first, the circuit produces the two's complement negation of the input on output z , one bit per clock cycle, least significant bit first. The input number can be any length; input y is 1 for all but the final bit of x , and 0 for just the final bit. Then the circuit is reset ready to start a new input number.
This is the end of the preview.
access the rest of the document.
Least significant bit, IEEE single-precision floating-point