Lecture24_PLL_CDR_2up - How do we set the clock at the best...

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EECS240 – Spring 2009 Lecture 24: PLL and CDR Overview Elad Alon Dept. of EECS EECS240 Lecture 24 2 Clock Generation Typical (low-cost) crystals give <500 MHz clock 5 Gb/s link Æ where to get a 5 GHz clock? PLL: multiply frequency up, align phase While maintaining low jitter, power 2 ÷N
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EECS240 Lecture 24 3 PLL: Linear Model ÷N EECS240 Lecture 24 4 Linear Model cont’d 4
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EECS240 Lecture 24 5 Stability and Loop Bandwidth 5 EECS240 Lecture 24 6 Loop Components: Phase Detectors Basic idea: create pulses with width α to phase difference
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EECS240 Lecture 24 7 Loop Filter 7 EECS240 Lecture 24 8 VCOs 8
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EECS240 Lecture 24 9 Noise and Jitter 9 EECS240 Lecture 24 10 Clock Recovery Voltage margin strongly dependent on exact sampling position
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Unformatted text preview: How do we set the clock at the best place? 10 Skewed Ideal EECS240 Lecture 24 11 Conceptual CDR 11 EECS240 Lecture 24 12 System Types (Source) Synchronous Same frequency &amp; phase Mesochronous Same frequency, unknown phase Plesiochronous Almost same frequency 12 * From EE371, Stanford University EECS240 Lecture 24 13 Linear (Hogge) Phase Detector EECS240 Lecture 24 14 Bang-Bang (Alexander) Phase Detector Edge clock T sym /2 away from data Derive early/late from data and edge samples: Dn: (d n != e n ) &amp; (d n-1 != d n ) Up: (d n == e n ) &amp; (d n-1 != d n ) 14 edge Clk data Clk d n e n V in...
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Lecture24_PLL_CDR_2up - How do we set the clock at the best...

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